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References: <20230624131632.2972546-1-bigunclemax@gmail.com>
 <20230624131632.2972546-4-bigunclemax@gmail.com> <10311404.nUPlyArG6x@jernej-laptop>
In-Reply-To: <10311404.nUPlyArG6x@jernej-laptop>
From:   Maxim Kiselev <bigunclemax@gmail.com>
Date:   Mon, 31 Jul 2023 18:22:11 +0300
Message-ID: <CALHCpMgXy0pLiVR8V48Roi82EJ7Zrx-Xyc-6etjgkmN0B7pb8A@mail.gmail.com>
Subject: Re: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for
 pinmux PC port
To:     =?UTF-8?Q?Jernej_=C5=A0krabec?= <jernej.skrabec@gmail.com>
Cc:     linux-spi@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Chen-Yu Tsai <wens@csie.org>,
        Samuel Holland <samuel@sholland.org>,
        Mark Brown <broonie@kernel.org>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org
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=D0=BF=D0=BD, 31 =D0=B8=D1=8E=D0=BB. 2023=E2=80=AF=D0=B3. =D0=B2 01:30, Jer=
nej =C5=A0krabec <jernej.skrabec@gmail.com>:
>
> Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a):
> > Add pinmux node that describes pins on PC port which required for
> > QSPI mode.
> >
> > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
> > ---
> >  arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> > 1bb1e5cae602..9f754dd03d85 100644
> > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
> >                               pins =3D "PB6", "PB7";
> >                               function =3D "uart3";
> >                       };
> > +
> > +                     /omit-if-no-ref/
> > +                     qspi0_pc_pins: qspi0-pc-pins {
> > +                             pins =3D "PC2", "PC3", "PC4", "PC5",
> "PC6",
> > +                                    "PC7";
> > +                             function =3D "spi0";
> > +                     };
>
> Sorry for late review, but it seems I'm missing something. D1 manual says
> those are pins for ordinary SPI, with HOLD and WP signals. Can they be
> repurposed for quad SPI?
>
Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI
Quad-Input/Quad-Output Mode):
"Using the quad mode allows data to be transferred to or from the
device at 4 times the rate of standard single mode, the data can be
read
at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3
(HOLD#)) at the same time."