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Date:   Tue, 1 Aug 2023 11:12:05 +0800
From:   Zhenyu Wang <zhenyuw@linux.intel.com>
To:     Yan Zhao <yan.y.zhao@intel.com>
Cc:     intel-gfx@lists.freedesktop.org,
        intel-gvt-dev@lists.freedesktop.org, linux-kernel@vger.kernel.org,
        zhi.a.wang@intel.com, zhenyuw@linux.intel.com, kvm@vger.kernel.org
Subject: Re: [PATCH] drm/i915/gvt: Fix bug in getting msg length in AUX CH
 registers handler
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Reply-To: Zhenyu Wang <zhenyuw@linux.intel.com>
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On 2023.07.31 19:20:33 +0800, Yan Zhao wrote:
> Msg length should be obtained from value written to AUX_CH_CTL register
> rather than from enum type of the register.
>=20
> Commit 0cad796a2269  ("drm/i915: Use REG_BIT() & co. for AUX CH registers=
")
> incorrectly calculates the msg_length from reg type and yields below
> warning in intel_gvt_i2c_handle_aux_ch_write():
> "i915 0000:00:02.0: drm_WARN_ON(msg_length !=3D 4)".
>=20
> Fixes: 0cad796a2269 ("drm/i915: Use REG_BIT() & co. for AUX CH registers")
> Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
> ---

Thanks for the fix!

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

>  drivers/gpu/drm/i915/gvt/edid.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/e=
did.c
> index 2a0438f12a14..af9afdb53c7f 100644
> --- a/drivers/gpu/drm/i915/gvt/edid.c
> +++ b/drivers/gpu/drm/i915/gvt/edid.c
> @@ -491,7 +491,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_v=
gpu *vgpu,
>  		return;
>  	}
> =20
> -	msg_length =3D REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, reg);
> +	msg_length =3D REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);
> =20
>  	// check the msg in DATA register.
>  	msg =3D vgpu_vreg(vgpu, offset + 4);
> --=20
> 2.17.1
>=20

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