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Date:   Tue, 1 Aug 2023 08:23:23 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Yinbo Zhu <zhuyinbo@loongson.cn>
Cc:     Linus Walleij <linus.walleij@linaro.org>,
        Bartosz Golaszewski <brgl@bgdev.pl>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>, linux-gpio@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Jianmin Lv <lvjianmin@loongson.cn>, wanghongliang@loongson.cn,
        Liu Peibao <liupeibao@loongson.cn>,
        loongson-kernel@lists.loongnix.cn
Subject: Re: [PATCH v2 1/2] gpio: dt-bindings: add parsing of loongson gpio
 offset
Message-ID: <20230801-whenever-imitation-b2759b212f6b@spud>
References: <20230731091059.17323-1-zhuyinbo@loongson.cn>
 <20230731091059.17323-2-zhuyinbo@loongson.cn>
 <20230731-setback-such-61815ee3ef51@spud>
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On Tue, Aug 01, 2023 at 02:39:49PM +0800, Yinbo Zhu wrote:
>=20
>=20
> =E5=9C=A8 2023/7/31 =E4=B8=8B=E5=8D=8811:55, Conor Dooley =E5=86=99=E9=81=
=93:
> > On Mon, Jul 31, 2023 at 05:10:58PM +0800, Yinbo Zhu wrote:
> > > Add parsing GPIO configure, input, output, interrupt register offset
> > > address and GPIO control mode support.
> >=20
> > This reeks of insufficient use of SoC specific compatibles. Do GPIO
> > controllers on the same SoC have different register offsets?
>=20
>=20
> Yes,
>=20
> > Where are the users for this?
>=20
>=20
> For example, ls2k500 contains multiple GPIO chips with different
> (configure, input, output, interrupt) offset addresses, but all others
> are the same.

Right. That's admittedly not what I expected to hear! Can you firstly
explain this in the commit message, and secondly add a soc-specific
compatible for the ls2k500 and only allow these properties on that SoC?

Thanks,
Conor.

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