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From:   WANG Xuerui <kernel@xen0n.name>
To:     Song Liu <song@kernel.org>
Cc:     Huacai Chen <chenhuacai@kernel.org>, linux-raid@vger.kernel.org,
        loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
        WANG Xuerui <git@xen0n.name>
Subject: [PATCH 0/3] raid5, raid6: Accelerate RAID math with LoongArch SIMD
Date:   Tue,  1 Aug 2023 16:13:32 +0800
Message-Id: <20230801081335.523097-1-kernel@xen0n.name>
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From: WANG Xuerui <git@xen0n.name>

Hi,

Seeing the LoongArch port recently (finally!) gained the ability to use
the vector units, I've subsequently ported the RAID5/6 math to LSX and
LASX (which are LoongArch's 128-bit and 256-bit SIMD extensions), with
nice speedups observed. They are reasonably straight-forward conversions
of existing code, and I hope the comments I put in there are helpful
enough for anyone not familiar with LoongArch assembly to get a rough
picture of how things work here. Performance numbers are included in
each commit's commit message.

This series needs [1] ("LoongArch: Allow usage of LSX/LASX in the
kernel") as a prerequisite, or the vector context would likely get
corrupted by the vector-unaware kernel_fpu_{begin,end} calls. I tested
the changes on top of next-20230731 with the raid6test build fixes [2]
applied, but the series should apply cleanly to v6.5-rc4 (or maybe any
other tag) too.

[1]: https://lore.kernel.org/loongarch/20230722072201.2677516-1-chenhuacai@loongson.cn/
[2]: https://lore.kernel.org/linux-raid/20230731104911.411964-1-kernel@xen0n.name/

WANG Xuerui (3):
  LoongArch: Add SIMD-optimized XOR routines
  raid6: Add LoongArch SIMD syndrome calculation
  raid6: Add LoongArch SIMD recovery implementation

 arch/loongarch/include/asm/xor.h      |  68 ++++
 arch/loongarch/include/asm/xor_simd.h |  42 +++
 arch/loongarch/lib/Makefile           |   3 +
 arch/loongarch/lib/xor_simd.c         |  92 +++++
 arch/loongarch/lib/xor_simd.h         |  46 +++
 arch/loongarch/lib/xor_simd_glue.c    |  71 ++++
 arch/loongarch/lib/xor_template.c     | 109 ++++++
 include/linux/raid/pq.h               |   4 +
 lib/raid6/Makefile                    |   1 +
 lib/raid6/algos.c                     |  16 +
 lib/raid6/loongarch.h                 |  38 ++
 lib/raid6/loongarch_simd.c            | 417 +++++++++++++++++++++
 lib/raid6/recov_loongarch_simd.c      | 501 ++++++++++++++++++++++++++
 lib/raid6/test/Makefile               |  12 +
 14 files changed, 1420 insertions(+)
 create mode 100644 arch/loongarch/include/asm/xor.h
 create mode 100644 arch/loongarch/include/asm/xor_simd.h
 create mode 100644 arch/loongarch/lib/xor_simd.c
 create mode 100644 arch/loongarch/lib/xor_simd.h
 create mode 100644 arch/loongarch/lib/xor_simd_glue.c
 create mode 100644 arch/loongarch/lib/xor_template.c
 create mode 100644 lib/raid6/loongarch.h
 create mode 100644 lib/raid6/loongarch_simd.c
 create mode 100644 lib/raid6/recov_loongarch_simd.c


base-commit: 5d0c230f1de8c7515b6567d9afba1f196fb4e2f4
prerequisite-patch-id: 85d08a9828893250ae78dbca9d6e6f8dac755f61
prerequisite-patch-id: fe0bba41e0bbc676454365ed16fb13fc0aac6ee0
prerequisite-patch-id: 84ef8212b74e696ce019255bbfd9679d7516f7f7
prerequisite-patch-id: b1f8fc4e4acdaff7f821a9fcbd063475178e037b
prerequisite-patch-id: 82aacbf27f249fdefe40dd6bcc712e5795256926
prerequisite-patch-id: ae4e026e18f92ffcc93f6b135a3bd48fbdded39a
-- 
2.40.0