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Subject: Re: [PATCH] LoongArch: Fixup cmpxchg sematic for memory barrier
From:   Xi Ruoyao <xry111@xry111.site>
To:     Guo Ren <guoren@kernel.org>, WANG Rui <wangrui@loongson.cn>
Cc:     chenhuacai@kernel.or, kernel@xen0n.name, arnd@arndb.de,
        andi.shyti@linux.intel.com, andrzej.hajda@intel.com,
        peterz@infradead.org, will@kernel.org, boqun.feng@gmail.com,
        mark.rutland@arm.com, loongarch@lists.linux.dev,
        linux-kernel@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>
Date:   Tue, 01 Aug 2023 19:23:00 +0800
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On Tue, 2023-08-01 at 18:49 +0800, Guo Ren wrote:
> > On Tue, Aug 1, 2023 at 5:05=E2=80=AFPM Guo Ren <guoren@kernel.org> wrot=
e:
> > >=20
> > > > The CoRR problem would cause wider problems than this.For this case=
,
> > > > do you mean your LL -> LL would be reordered?
> > > >=20
> > > > CPU 0
> > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU1
> > > > LL(2) (set ex-monitor)
> > > >=20
> > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 store (break the ex-monitor)
> > > > LL(1) (reordered instruction set ex-monitor
> > > > SC(3) (successes ?)
> > > Sorry for the mail client reformat, I mean:
> > >=20
> > > CPU0=C2=A0 LL(2) (set ex-monitor)
> > > CPU1=C2=A0 STORE (break the ex-monitor)
> > > CPU0=C2=A0 LL(1) (reordered instruction set ex-monitor
> > > CPU0=C2=A0 SC(3) (success?)
> >=20
> > No. LL and LL won't reorder because LL implies a memory barrier(though
> > not acquire semantics).
> That means we could remove __WEAK_LLSC_MB totally, right?

As I've said, to implement CAS on LA464 this barrier is *really* needed.
I initially didn't believe it then I spent one night (from 11 PM to 04
AM) debugging GCC libgomp test failures.

On LA664 (3A6000) things may change though.

--=20
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University