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Tue, 1 Aug 2023 04:44:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CCA596156E; Tue, 1 Aug 2023 11:44:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B0C58C433C8; Tue, 1 Aug 2023 11:44:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690890280; bh=dbodHSwIgKgpR708XhGtQfRJC68lUns//VtMieKP9nc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=mIPN/0FlrywKoIvGuj184pORf/lD8hhwluBTGh+LkJQPCLledF7sFrBYwGV/lqUS1 523bB6efo7rFR3KMuWoIJhQr4Bdcgm9DWfXIm7yGqW2lahDabJWA2iv5BlA4oi9H6I E1J608KbtQ3ZReXwf9vUfA6ouEDGz27xA4f6lSvhMoRmPdcW72n4i/q07LTV+DtI4k khUoBRy5gFFucKponYrQlQ2svb9z4sncsgjZNL59SYR06uNZWn9aiJbYOEgGForKMM ve6Ez9aeP1r+xBgk7F+Ee+2DMbgCNEv20Uz60Ak6AlyqGQ5nxLVj8l+HlfWckYM9BT haR5vtYw/l+kA== Date: Tue, 1 Aug 2023 13:44:37 +0200 From: Maxime Ripard To: Keith Zhao Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Palmer Dabbelt , Albert Ou , Maarten Lankhorst , Thomas Zimmermann , Philipp Zabel , Sumit Semwal , christian.koenig@amd.com, Bjorn Andersson , Heiko Stuebner , Shawn Guo , Jagan Teki , Chris Morgan , Jack Zhu , Shengyang Chen , Changhuang Liang Subject: Re: [PATCH v1 v1 2/7] dt-bindings: display: Add yamls for JH7110 display system Message-ID: References: <20230801101030.2040-1-keith.zhao@starfivetech.com> <20230801101030.2040-3-keith.zhao@starfivetech.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="dan5yrpicomxdg2s" Content-Disposition: inline In-Reply-To: <20230801101030.2040-3-keith.zhao@starfivetech.com> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --dan5yrpicomxdg2s Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, On Tue, Aug 01, 2023 at 06:10:25PM +0800, Keith Zhao wrote: > diff --git a/Documentation/devicetree/bindings/display/starfive/starfive,jh7110-dc8200.yaml b/Documentation/devicetree/bindings/display/starfive/starfive,jh7110-dc8200.yaml > new file mode 100644 > index 000000000..bebe2050c > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/starfive/starfive,jh7110-dc8200.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/starfive/starfive,jh7110-dc8200.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive display controller > + > +description: > + The StarFive SoC uses the display controller based on Verisilicon IP > + to transfer the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Keith Zhao > + > +properties: > + compatible: > + const: starfive,jh7110-dc8200 > + > + reg: > + maxItems: 3 What these registers are used for must be documented. > + > + interrupts: > + items: > + - description: The interrupt will be generated when DC finish one frame > + > + clocks: > + items: > + - description: Clock for display system noc bus. > + - description: Pixel clock for display channel 0. > + - description: Pixel clock for display channel 1. > + - description: Clock for axi interface of display controller. > + - description: Core clock for display controller. > + - description: Clock for ahb interface of display controller. > + - description: External HDMI pixel clock. > + - description: Parent clock for pixel clock > + > + clock-names: > + items: > + - const: vout_noc_disp > + - const: vout_pix0 > + - const: vout_pix1 > + - const: vout_axi > + - const: vout_core > + - const: vout_vout_ahb > + - const: hdmitx0_pixel > + - const: vout_dc8200 The clock-names should reflect what they are used for on the device, not what their name is in the system. So it should rather be something like "noc-bus", "channel0", "channel1", etc. vout, or the soc model, shouldn't appear there. > + resets: > + items: > + - description: Reset for axi interface of display controller. > + - description: Reset for ahb interface of display controller. > + - description: Core reset of display controller. > + > + reset-names: > + items: > + - const: vout_axi > + - const: vout_ahb > + - const: vout_core Ditto. Also, I'm a bit confused, how can a device be attached to both an AXI and AHB bus? That, plus the multiple registers spaces, make me think that this is multiple devices glued together in a single node, which isn't ok. > + port: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + A port node with endpoint definitions as defined in > + Documentation/devicetree/bindings/media/video-interfaces.txt. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - resets > + - reset-names > + - port > + > +additionalProperties: false > + > +examples: > + - | > + dc8200: lcd-controller@29400000 { > + compatible = "starfive,jh7110-dc8200"; > + reg = <0x29400000 0x100>, <0x29400800 0x2000>, <0x295b0000 0x90>; > + interrupts = <95>; > + clocks = <&syscrg 60>, > + <&voutcrg 7>, > + <&voutcrg 8>, > + <&voutcrg 4>, > + <&voutcrg 5>, > + <&voutcrg 6>, > + <&hdmitx0_pixelclk>, > + <&voutcrg 1>; > + clock-names = "vout_noc_disp", "vout_pix0", "vout_pix1", > + "vout_axi", "vout_core", "vout_vout_ahb", > + "hdmitx0_pixel","vout_dc8200"; > + resets = <&voutcrg 0>, <&voutcrg 1>, <&voutcrg 2>; > + reset-names = "vout_axi", "vout_ahb", "vout_core"; > + dc_out: port { > + #address-cells = <1>; > + #size-cells = <0>; > + dc_out_hdmi: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&hdmi_in_dc>; > + }; > + }; > + }; > diff --git a/Documentation/devicetree/bindings/display/starfive/starfive,jh7110-inno-hdmi.yaml b/Documentation/devicetree/bindings/display/starfive/starfive,jh7110-inno-hdmi.yaml > new file mode 100644 > index 000000000..f6927acf6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/starfive/starfive,jh7110-inno-hdmi.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/starfive/starfive,jh7110-inno-hdmi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Starfive JH7110 HDMI controller > + > +description: > + The StarFive JH7110 SoC uses the HDMI signal transmiter based on innosilicon IP > + to generate HDMI signal from its input and transmit the signal to the screen. > + > +maintainers: > + - Keith Zhao > + > +properties: > + compatible: > + const: "starfive,jh7110-inno-hdmi" > + > + reg: > + minItems: 1 > + > + interrupts: > + items: > + - description: The HDMI hot plug detection interrupt. > + > + clocks: > + items: > + - description: System clock of HDMI module. > + - description: Mclk clock of HDMI audio. > + - description: Bclk clock of HDMI audio. > + - description: Pixel clock generated by HDMI module. > + > + clock-names: > + items: > + - const: sysclk > + - const: mclk > + - const: bclk > + - const: pclk > + > + resets: > + items: > + - description: Reset for HDMI module. > + > + reset-names: > + items: > + - const: hdmi_tx If there's only one you don't need reset-names Maxime --dan5yrpicomxdg2s Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCZMjwJQAKCRDj7w1vZxhR xZBQAPwPOEedmxWZJ27iqcESJscaRD6CHACzB6No3CR39QnaDgD/bbKScqVg2wHb dTG9DGpqq1ezLI5zfPLEM3steJgVlg4= =A6ek -----END PGP SIGNATURE----- --dan5yrpicomxdg2s--