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Date:   Tue, 1 Aug 2023 19:50:07 +0200
From:   Sebastian Reichel <sebastian.reichel@collabora.com>
To:     Elaine Zhang <zhangqing@rock-chips.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org,
        kever.yang@rock-chips.com, heiko@sntech.de,
        linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org,
        linux-kernel@vger.kernel.org, huangtao@rock-chips.com
Subject: Re: [RESEND PATCH v2 0/3] clk: rockchip: add GATE_LINK
Message-ID: <20230801175007.kd5j3c6ygjyn5wh5@mercury.elektranox.org>
References: <20230801074357.10770-1-zhangqing@rock-chips.com>
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Hi,

On Tue, Aug 01, 2023 at 03:43:54PM +0800, Elaine Zhang wrote:
> Recent Rockchip SoCs have a new hardware block called Native Interface
> Unit (NIU), which gates clocks to devices behind them. These effectively
> need two parent clocks.
> Use GATE_LINK to handle this.
>=20
> change in V2:
> [PATCH v2 1/3]: fix reported warnings
> [PATCH v2 2/3]: Bindings submit independent patches
> [PATCH v2 3/3]: fix reported warnings
>=20
> Elaine Zhang (3):
>   clk: rockchip: add support for gate link
>   dt-bindings: clock: rk3588: export PCLK_VO1GRF clk id
>   clk: rockchip: rk3588: Adjust the GATE_LINK parameter
>=20
>  drivers/clk/rockchip/Makefile                 |   1 +
>  drivers/clk/rockchip/clk-gate-link.c          | 189 ++++++++++++++++++
>  drivers/clk/rockchip/clk-rk3588.c             | 110 +++++-----
>  drivers/clk/rockchip/clk.c                    |   7 +
>  drivers/clk/rockchip/clk.h                    |  22 ++
>  .../dt-bindings/clock/rockchip,rk3588-cru.h   |   3 +-
>  6 files changed, 280 insertions(+), 52 deletions(-)
>  create mode 100644 drivers/clk/rockchip/clk-gate-link.c

The series is

Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>

-- Sebastian

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