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Date:   Tue, 1 Aug 2023 21:57:43 +0100
From:   Conor Dooley <conor@kernel.org>
To:     niravkumar.l.rabara@intel.com
Cc:     adrian.ho.yin.ng@intel.com, andrew@lunn.ch, conor+dt@kernel.org,
        devicetree@vger.kernel.org, dinguyen@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org, mturquette@baylibre.com,
        netdev@vger.kernel.org, p.zabel@pengutronix.de,
        richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
        wen.ping.teh@intel.com
Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock
 manager
Message-ID: <20230801-handball-glorifier-e55d44a2b638@spud>
References: <20230618132235.728641-1-niravkumar.l.rabara@intel.com>
 <20230801010234.792557-1-niravkumar.l.rabara@intel.com>
 <20230801010234.792557-4-niravkumar.l.rabara@intel.com>
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On Tue, Aug 01, 2023 at 09:02:32AM +0800, niravkumar.l.rabara@intel.com wro=
te:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>=20
> Add clock ID definitions for Intel Agilex5 SoCFPGA.
> The registers in Agilex5 handling the clock is named as clock manager.
>=20
> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  .../bindings/clock/intel,agilex5-clkmgr.yaml  |  41 +++++++
>  .../dt-bindings/clock/intel,agilex5-clkmgr.h  | 100 ++++++++++++++++++
>  2 files changed, 141 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5=
-clkmgr.yaml
>  create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h
>=20
> diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr=
=2Eyaml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> new file mode 100644
> index 000000000000..60e57a9fb939
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel SoCFPGA Agilex5 clock manager
> +
> +maintainers:
> +  - Dinh Nguyen <dinguyen@kernel.org>
> +
> +description:
> +  The Intel Agilex5 Clock Manager is an integrated clock controller, whi=
ch
> +  generates and supplies clock to all the modules.
> +
> +properties:
> +  compatible:
> +    const: intel,agilex5-clkmgr
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:

> +  # Clock controller node:

This comment seems utterly pointless.
Otherwise this looks okay to me.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> +  - |
> +    clkmgr: clock-controller@10d10000 {
> +      compatible =3D "intel,agilex5-clkmgr";
> +      reg =3D <0x10d10000 0x1000>;
> +      #clock-cells =3D <1>;
> +    };
> +...

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