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From:   "Rabara, Niravkumar L" <niravkumar.l.rabara@intel.com>
To:     Conor Dooley <conor@kernel.org>
CC:     "Ng, Adrian Ho Yin" <adrian.ho.yin.ng@intel.com>,
        "andrew@lunn.ch" <andrew@lunn.ch>,
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Subject: RE: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock
 manager
Thread-Topic: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock
 manager
Thread-Index: AQHZxBQYoDLOJHXuDEWKBojhTKBqcq/V7XmAgABmtRA=
Date:   Wed, 2 Aug 2023 03:06:51 +0000
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> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: Wednesday, 2 August, 2023 4:58 AM
> To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>
> Cc: Ng, Adrian Ho Yin <adrian.ho.yin.ng@intel.com>; andrew@lunn.ch;
> conor+dt@kernel.org; devicetree@vger.kernel.org; dinguyen@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; linux-clk@vger.kernel.org; linux-
> kernel@vger.kernel.org; Turquette, Mike <mturquette@baylibre.com>;
> netdev@vger.kernel.org; p.zabel@pengutronix.de; richardcochran@gmail.com;
> robh+dt@kernel.org; sboyd@kernel.org; wen.ping.teh@intel.com
> Subject: Re: [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock m=
anager
>=20
> On Tue, Aug 01, 2023 at 09:02:32AM +0800, niravkumar.l.rabara@intel.com
> wrote:
> > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> >
> > Add clock ID definitions for Intel Agilex5 SoCFPGA.
> > The registers in Agilex5 handling the clock is named as clock manager.
> >
> > Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
> > Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> > ---
> >  .../bindings/clock/intel,agilex5-clkmgr.yaml  |  41 +++++++
> > .../dt-bindings/clock/intel,agilex5-clkmgr.h  | 100 ++++++++++++++++++
> >  2 files changed, 141 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> >  create mode 100644 include/dt-bindings/clock/intel,agilex5-clkmgr.h
> >
> > diff --git
> > a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> > b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml
> > new file mode 100644
> > index 000000000000..60e57a9fb939
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yam
> > +++ l
> > @@ -0,0 +1,41 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Intel SoCFPGA Agilex5 clock manager
> > +
> > +maintainers:
> > +  - Dinh Nguyen <dinguyen@kernel.org>
> > +
> > +description:
> > +  The Intel Agilex5 Clock Manager is an integrated clock controller,
> > +which
> > +  generates and supplies clock to all the modules.
> > +
> > +properties:
> > +  compatible:
> > +    const: intel,agilex5-clkmgr
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
>=20
> > +  # Clock controller node:
>=20
> This comment seems utterly pointless.
> Otherwise this looks okay to me.
>=20
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>=20
> Thanks,
> Conor.
>=20

Removed in [PATCH v3 3/5].=20

Thanks,
Nirav

> > +  - |
> > +    clkmgr: clock-controller@10d10000 {
> > +      compatible =3D "intel,agilex5-clkmgr";
> > +      reg =3D <0x10d10000 0x1000>;
> > +      #clock-cells =3D <1>;
> > +    };
> > +...