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Message-ID: <386a727c-f845-c802-f4e3-8f727adfd2ad@quicinc.com>
Date:   Wed, 2 Aug 2023 10:38:22 +0530
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Subject: Re: [PATCH v1] arm64: dts: qcom: sc7280: Add PCIe0 node
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        <manivannan.sadhasivam@linaro.org>
CC:     <helgaas@kernel.org>, <linux-pci@vger.kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_vbadigan@quicinc.com>, <quic_nitegupt@quicinc.com>,
        <quic_skananth@quicinc.com>, <quic_ramkri@quicinc.com>,
        <quic_parass@quicinc.com>,
        "reviewer:ARM/QUALCOMM CHROMEBOOK SUPPORT" 
        <cros-qcom-dts-watchers@chromium.org>,
        Andy Gross <agross@kernel.org>,
        "Bjorn Andersson" <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
References: <1690540760-20191-1-git-send-email-quic_krichai@quicinc.com>
 <17c2ba50-3b72-523c-d92b-1ecbf9be7450@linaro.org>
 <f3d5c72d-90d3-b091-f995-5ad0bf93ae1d@quicinc.com>
 <a2024453-e749-b659-52a0-83ded8bb5c38@linaro.org>
 <1cfdf3c4-6e4f-e73d-c711-3890ceabb69d@quicinc.com>
 <0617841a-5d1f-b703-daa9-fedba148a05d@linaro.org>
From:   Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
In-Reply-To: <0617841a-5d1f-b703-daa9-fedba148a05d@linaro.org>
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On 7/31/2023 12:24 PM, Krzysztof Kozlowski wrote:
> On 31/07/2023 07:29, Krishna Chaitanya Chundru wrote:
>> On 7/28/2023 9:27 PM, Krzysztof Kozlowski wrote:
>>> On 28/07/2023 17:10, Krishna Chaitanya Chundru wrote:
>>>> On 7/28/2023 5:33 PM, Krzysztof Kozlowski wrote:
>>>>> On 28/07/2023 12:39, Krishna chaitanya chundru wrote:
>>>>>> Add PCIe dtsi node for PCIe0 controller on sc7280 platform.
>>>>>>
>>>>>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>>>>> Thank you for your patch. There is something to discuss/improve.
>>>>>
>>>>>
>>>>>> +		pcie0_phy: phy@1c06000 {
>>>>>> +			compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
>>>>>> +			reg = <0 0x01c06000 0 0x1c0>;
>>>>>> +			#address-cells = <2>;
>>>>>> +			#size-cells = <2>;
>>>>>> +			ranges;
>>>>>> +			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>>>>>> +				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>>>>>> +				 <&gcc GCC_PCIE_CLKREF_EN>,
>>>>>> +				 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
>>>>>> +			clock-names = "aux", "cfg_ahb", "ref", "refgen";
>>>>>> +
>>>>>> +			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>>>>>> +			reset-names = "phy";
>>>>>> +
>>>>>> +			assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
>>>>>> +			assigned-clock-rates = <100000000>;
>>>>>> +
>>>>>> +			status = "disabled";
>>>>>> +
>>>>>> +			pcie0_lane: phy@1c0e6200 {
>>>>> Isn't this old-style of bindings? Wasn't there a change? On what tree
>>>>> did you base it?
>>> The work was here:
>>> https://lore.kernel.org/all/20230324022514.1800382-5-dmitry.baryshkov@linaro.org/
>>>
>>> But I don't remember the status.
>>>
>>>> Let me rebase and send it again.
>>> This anyway looks like wrong compatible. You used sm8250.
>> The patch was send on latest linux-next only and the above change is not
>> merged yet.
> I don't think we will want old DTS syntax... but this actually depends
> on the status of Dmitry's patchset.

Kryzysztof, as the bindings also not yet merged shall we use old DTS 
syntax or shall I rebase on dmitry's patch and send it.

- KC

>
>> We are using the same compatible string as sm8250 because the phy is
>> same both from hardware and software perspective for sm8250.
>>
>> that is why we are using the same compatible string.
>>
>> Can you let me know if we want create a separate compatible string for
>> this even though  we are using same phy?
> https://elixir.bootlin.com/linux/v6.1-rc1/source/Documentation/devicetree/bindings/writing-bindings.rst#42
>
>
> Best regards,
> Krzysztof
>