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Date:   Wed, 2 Aug 2023 07:54:35 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Minda Chen <minda.chen@starfivetech.com>
CC:     Conor Dooley <conor@kernel.org>,
        Jisheng Zhang <jszhang@kernel.org>,
        Samuel Holland <samuel@sholland.org>,
        Dao Lu <daolu@rivosinc.com>, Heiko Stuebner <heiko@sntech.de>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v1] riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace
 zihintpause
Message-ID: <20230802-sharpness-spoon-f9b8804fb66f@wendy>
References: <20230802064215.31111-1-minda.chen@starfivetech.com>
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Hey Minda,

On Wed, Aug 02, 2023 at 02:42:15PM +0800, Minda Chen wrote:
> Actually it is a part of Conor's
> commit aae538cd03bc ("riscv: fix detection of toolchain
> Zihintpause support").
> It is looks like a merge issue.

Yup, spot on.

> Samuel's
> commit 0b1d60d6dd9e ("riscv: Fix build with
> CONFIG_CC_OPTIMIZE_FOR_SIZE=3Dy") do not base on Conor's commit and
> revert to __riscv_zihintpause. So this patch can fix it.
>=20
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>

Did you actually manage to trigger this, or was this by inspection?
clang-15 + binutils 2.35 was, IIRC, how we spotted this because that's
what the clang-built-linux CI uses to test the LTS kernels from before
LLVM's IAS was supported for RISC-V. Seemingly all that needs to be
satisfied there is that zihintpause doesn't appear in -march so this has
gone unnoticed.

Fixes: 3c349eacc559 ("Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE=
_FOR_SIZE=3Dy"")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> ---
>  arch/riscv/include/asm/vdso/processor.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include=
/asm/vdso/processor.h
> index 14f5d27783b8..96b65a5396df 100644
> --- a/arch/riscv/include/asm/vdso/processor.h
> +++ b/arch/riscv/include/asm/vdso/processor.h
> @@ -14,7 +14,7 @@ static inline void cpu_relax(void)
>  	__asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy));
>  #endif
> =20
> -#ifdef __riscv_zihintpause
> +#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
>  	/*
>  	 * Reduce instruction retirement.
>  	 * This assumes the PC changes.
> --=20
> 2.17.1
>=20

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