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Date:   Wed, 2 Aug 2023 08:02:15 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     <niravkumar.l.rabara@intel.com>
CC:     <adrian.ho.yin.ng@intel.com>, <andrew@lunn.ch>,
        <conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
        <dinguyen@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <mturquette@baylibre.com>, <netdev@vger.kernel.org>,
        <p.zabel@pengutronix.de>, <richardcochran@gmail.com>,
        <robh+dt@kernel.org>, <sboyd@kernel.org>, <wen.ping.teh@intel.com>
Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
 manager
Message-ID: <20230802-reuse-diffusion-d41ed8175390@wendy>
References: <20230801010234.792557-4-niravkumar.l.rabara@intel.com>
 <20230802025842.1260345-1-niravkumar.l.rabara@intel.com>
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On Wed, Aug 02, 2023 at 10:58:42AM +0800, niravkumar.l.rabara@intel.com wro=
te:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>=20
> Add clock ID definitions for Intel Agilex5 SoCFPGA.
> The registers in Agilex5 handling the clock is named as clock manager.
>=20
> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

Damn, I was too late - you already sent a v3 :/

However, there only seems to be a v3 of this one patch and it was sent
in reply to the v2 series? The normal thing to do is resend the entire
series, not just one patch, as a new thread. Not using a new thread may
make it harder to apply & will also bury the email in people's mailboxes
that use things like mutt. A single patch as a reply is also confusing,
as the rest of the v3 looks like it is missing!

Thanks,
Conor.

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