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Wed, 02 Aug 2023 10:33:27 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 372AXQU1029558 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Aug 2023 10:33:26 GMT Received: from [10.253.73.93] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 03:33:23 -0700 Message-ID: Date: Wed, 2 Aug 2023 18:33:20 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH 1/3] clk: Add the flag CLK_ENABLE_MUTEX_LOCK of enabling clock Content-Language: en-US To: Stephen Boyd , , , , , , , , CC: , , , , References: <20230801085352.22873-1-quic_luoj@quicinc.com> <20230801085352.22873-2-quic_luoj@quicinc.com> <02abeb64fb360245791b467b371f1491.sboyd@kernel.org> From: Jie Luo In-Reply-To: <02abeb64fb360245791b467b371f1491.sboyd@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: x9oFqgpz1mi4t-YF2X74ZeW9-okoVMUu X-Proofpoint-ORIG-GUID: x9oFqgpz1mi4t-YF2X74ZeW9-okoVMUu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_05,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 mlxlogscore=716 bulkscore=0 suspectscore=0 clxscore=1015 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020093 X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/2/2023 3:18 AM, Stephen Boyd wrote: > Quoting Luo Jie (2023-08-01 01:53:50) >> Support the clock controller where the HW register is >> accessed by MDIO bus, the spin lock can't be used because >> of sleep during the MDIO operation. >> >> Add the flag CLK_ENABLE_MUTEX_LOCK to hint clock framework >> to use mutex lock instead of the spin lock. > > Why can't you enable the MDIO bus clk in .prepare()? thanks Stephen for the suggestion, let me check this and update patchset.