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Date:   Wed, 02 Aug 2023 16:58:21 +0100
Message-ID: <875y5xqvvm.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Raghavendra Rao Ananta <rananta@google.com>
Cc:     Oliver Upton <oliver.upton@linux.dev>,
        James Morse <james.morse@arm.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Sean Christopherson <seanjc@google.com>,
        Huacai Chen <chenhuacai@kernel.org>,
        Zenghui Yu <yuzenghui@huawei.com>,
        Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@atishpatra.org>,
        Jing Zhang <jingzhangos@google.com>,
        Reiji Watanabe <reijiw@google.com>,
        Colton Lewis <coltonlewis@google.com>,
        David Matlack <dmatlack@google.com>,
        linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
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        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        kvm@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>,
        Gavin Shan <gshan@redhat.com>,
        Shaoqin Huang <shahuang@redhat.com>
Subject: Re: [PATCH v7 06/12] arm64: tlb: Refactor the core flush algorithm of __flush_tlb_range
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On Mon, 31 Jul 2023 18:36:47 +0100,
Raghavendra Rao Ananta <rananta@google.com> wrote:
>=20
> On Thu, Jul 27, 2023 at 3:58=E2=80=AFAM Marc Zyngier <maz@kernel.org> wro=
te:
> >
> > On Sat, 22 Jul 2023 03:22:45 +0100,
> > Raghavendra Rao Ananta <rananta@google.com> wrote:
> > >
> > > Currently, the core TLB flush functionality of __flush_tlb_range()
> > > hardcodes vae1is (and variants) for the flush operation. In the
> > > upcoming patches, the KVM code reuses this core algorithm with
> > > ipas2e1is for range based TLB invalidations based on the IPA.
> > > Hence, extract the core flush functionality of __flush_tlb_range()
> > > into its own macro that accepts an 'op' argument to pass any
> > > TLBI operation, such that other callers (KVM) can benefit.
> > >
> > > No functional changes intended.
> > >
> > > Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
> > > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> > > Reviewed-by: Gavin Shan <gshan@redhat.com>
> > > Reviewed-by: Shaoqin Huang <shahuang@redhat.com>
> > > ---
> > >  arch/arm64/include/asm/tlbflush.h | 109 +++++++++++++++-------------=
--
> > >  1 file changed, 56 insertions(+), 53 deletions(-)
> > >
> > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/a=
sm/tlbflush.h
> > > index 412a3b9a3c25..f7fafba25add 100644
> > > --- a/arch/arm64/include/asm/tlbflush.h
> > > +++ b/arch/arm64/include/asm/tlbflush.h
> > > @@ -278,14 +278,62 @@ static inline void flush_tlb_page(struct vm_are=
a_struct *vma,
> > >   */
> > >  #define MAX_TLBI_OPS PTRS_PER_PTE
> > >
> > > +/* When the CPU does not support TLB range operations, flush the TLB
> > > + * entries one by one at the granularity of 'stride'. If the TLB
> > > + * range ops are supported, then:
> >
> > Comment format (the original was correct).
> >
> Isn't the format the same as original? Or are you referring to the
> fact that it needs to be placed inside the macro definition?

No, I'm referring to the multiline comment that starts with:

	/*  When the CPU does not support TLB range operations...

instead of the required:

	/*
	 * When the CPU does not support TLB range operations

which was correct before the coment was moved.

Thanks,

	M.

--=20
Without deviation from the norm, progress is not possible.