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From:   Jernej =?utf-8?B?xaBrcmFiZWM=?= <jernej.skrabec@gmail.com>
To:     Maxim Kiselev <bigunclemax@gmail.com>
Cc:     linux-spi@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Chen-Yu Tsai <wens@csie.org>,
        Samuel Holland <samuel@sholland.org>,
        Mark Brown <broonie@kernel.org>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 3/3] riscv: dts: allwinner: d1: Add QSPI pins node for pinmux
 PC port
Date:   Wed, 02 Aug 2023 21:50:39 +0200
Message-ID: <5956489.lOV4Wx5bFT@jernej-laptop>
In-Reply-To: <CALHCpMgXy0pLiVR8V48Roi82EJ7Zrx-Xyc-6etjgkmN0B7pb8A@mail.gmail.com>
References: <20230624131632.2972546-1-bigunclemax@gmail.com>
 <10311404.nUPlyArG6x@jernej-laptop>
 <CALHCpMgXy0pLiVR8V48Roi82EJ7Zrx-Xyc-6etjgkmN0B7pb8A@mail.gmail.com>
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Dne ponedeljek, 31. julij 2023 ob 17:22:11 CEST je Maxim Kiselev napisal(a):
> =D0=BF=D0=BD, 31 =D0=B8=D1=8E=D0=BB. 2023=E2=80=AF=D0=B3. =D0=B2 01:30, J=
ernej =C5=A0krabec <jernej.skrabec@gmail.com>:
> > Dne sobota, 24. junij 2023 ob 15:16:24 CEST je Maksim Kiselev napisal(a=
):
> > > Add pinmux node that describes pins on PC port which required for
> > > QSPI mode.
> > >=20
> > > Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
> > > ---
> > >=20
> > >  arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > >=20
> > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> > > 1bb1e5cae602..9f754dd03d85 100644
> > > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > > @@ -131,6 +131,13 @@ uart3_pb_pins: uart3-pb-pins {
> > >=20
> > >                               pins =3D "PB6", "PB7";
> > >                               function =3D "uart3";
> > >                      =20
> > >                       };
> > >=20
> > > +
> > > +                     /omit-if-no-ref/
> > > +                     qspi0_pc_pins: qspi0-pc-pins {
> > > +                             pins =3D "PC2", "PC3", "PC4", "PC5",
> >=20
> > "PC6",
> >=20
> > > +                                    "PC7";
> > > +                             function =3D "spi0";
> > > +                     };
> >=20
> > Sorry for late review, but it seems I'm missing something. D1 manual sa=
ys
> > those are pins for ordinary SPI, with HOLD and WP signals. Can they be
> > repurposed for quad SPI?
>=20
> Yes, they can. Here is a quote from D1 datasheet (9.3.3.8 SPI
> Quad-Input/Quad-Output Mode):
> "Using the quad mode allows data to be transferred to or from the
> device at 4 times the rate of standard single mode, the data can be
> read
> at fast speed using four data bits (MOSI, MISO, IO2 (WP#) and IO3
> (HOLD#)) at the same time."

Alright then.

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej