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Date:   Wed, 2 Aug 2023 13:55:29 -0700
From:   Jacob Pan <jacob.jun.pan@linux.intel.com>
To:     Jason Gunthorpe <jgg@nvidia.com>
Cc:     LKML <linux-kernel@vger.kernel.org>, iommu@lists.linux.dev,
        Lu Baolu <baolu.lu@linux.intel.com>,
        Joerg Roedel <joro@8bytes.org>,
        Jean-Philippe Brucker <jean-philippe@linaro.com>,
        Robin Murphy <robin.murphy@arm.com>,
        Will Deacon <will@kernel.org>,
        "Tian, Kevin" <kevin.tian@intel.com>, Yi Liu <yi.l.liu@intel.com>,
        "Yu, Fenghua" <fenghua.yu@intel.com>,
        Tony Luck <tony.luck@intel.com>, jacob.jun.pan@linux.intel.com
Subject: Re: [PATCH v11 2/8] iommu: Move global PASID allocation from SVA to
 core
Message-ID: <20230802135529.7a4ed681@jacob-builder>
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        <20230724222538.3902553-3-jacob.jun.pan@linux.intel.com>
        <ZMpsr3FbcEYRs/G8@nvidia.com>
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Hi Jason,

On Wed, 2 Aug 2023 11:48:15 -0300, Jason Gunthorpe <jgg@nvidia.com> wrote:

> On Mon, Jul 24, 2023 at 03:25:32PM -0700, Jacob Pan wrote:
> > Global PASID can be used beyond SVA. For example, drivers that use
> > Intel ENQCMD to submit work must use global PASIDs in that PASID
> > is stored in a per CPU MSR. When such device need to submit work
> > for in-kernel DMA with PASID, it must allocate PASIDs from the same
> > global number space to avoid conflict.  
> 
> This is a bit misleading, maybe:
> 
> ==
> Intel ENQCMD requires a single PASID to be shared between multiple
> devices, as the PASID is stored in a single MSR register per-process
> and userspace can use only that one PASID.
> 
> This means that the PASID allocation for any ENQCMD using device driver
> must always come from a shared global pool, regardless of what kind of
> domain the PASID will be used with.
> 
> Split the code for the global PASID allocator into
> iommu_alloc/free_global_pasid() so that drivers can attach non-SVA
> domains to PASIDs as well.
> ==
Much better. Let me update.

Thanks,

Jacob