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Date:   Thu, 3 Aug 2023 07:26:08 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Samuel Holland <samuel.holland@sifive.com>
CC:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        <linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
        Palmer Dabbelt <palmer@rivosinc.com>
Subject: Re: [PATCH] riscv: Fix CPU feature detection with SMP disabled
Message-ID: <20230803-bash-spree-4c02a339a6d5@wendy>
References: <20230803012608.3540081-1-samuel.holland@sifive.com>
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On Wed, Aug 02, 2023 at 06:26:06PM -0700, Samuel Holland wrote:
> commit 914d6f44fc50 ("RISC-V: only iterate over possible CPUs in ISA
> string parser") changed riscv_fill_hwcap() from iterating over CPU DT
> nodes to iterating over logical CPU IDs. Since this function runs long
> before cpu_dev_init() creates CPU devices, it hits the fallback path in
> of_cpu_device_node_get(), which itself iterates over the DT nodes,
> searching for a node with the requested CPU ID.

> (Incidentally, this
> makes riscv_fill_hwcap() now take quadratic time.)

Ouch, that I did not realise. Should we revert that portion of the
changes? Starting to sound like we should..

> riscv_fill_hwcap() passes a logical CPU ID to of_cpu_device_node_get(),
> which uses the arch_match_cpu_phys_id() hook to translate the logical ID
> to a physical ID as found in the DT.
>=20
> arch_match_cpu_phys_id() has a generic weak definition, and RISC-V
> provides a strong definition using cpuid_to_hartid_map(). However, the
> RISC-V specific implementation is located in arch/riscv/kernel/smp.c,
> and that file is only compiled when SMP is enabled.
>=20
> As a result, when SMP is disabled, the generic definition is used, and
> riscv_isa gets initialized based on the ISA string of hart 0, not the
> boot hart. On FU740, this means has_fpu() returns false, and userspace
> crashes when trying to use floating-point instructions.
>=20
> Fix this by moving arch_match_cpu_phys_id() to a file which is always
> compiled.
>=20
> Fixes: 70114560b285 ("RISC-V: Add RISC-V specific arch_match_cpu_phys_id")
> Fixes: 914d6f44fc50 ("RISC-V: only iterate over possible CPUs in ISA stri=
ng parser")
> Reported-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks for fixing this Samuel.

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