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Message-ID: <8e0623921f52113735d32f184f26e888e4e4e463.camel@redhat.com>
Subject: Re: [RFC PATCH 1/1] riscv/atomic.h: Deduplicate arch_atomic.*
From:   Leonardo =?ISO-8859-1?Q?Br=E1s?= <leobras@redhat.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>
Cc:     Palmer Dabbelt <palmer@rivosinc.com>,
        Will Deacon <will@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Boqun Feng <boqun.feng@gmail.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Date:   Thu, 03 Aug 2023 03:13:58 -0300
In-Reply-To: <CAJ6HWG7kvWtZHTBMiFAQriUn84E8SYuGmtAGmW8YVwqUyoUYgQ@mail.gmail.com>
References: <20230419062505.257231-1-leobras@redhat.com>
         <CAJ6HWG6nPdUQ_2_fSj6J7ZE7FB-T+VWT-kq9oW8BLTUtuQEWxA@mail.gmail.com>
         <CAJF2gTRZO2hogUbZvj0f41JJvmqLNz-MKTHJshgdhNMpp9Bc8w@mail.gmail.com>
         <CAJ6HWG7kvWtZHTBMiFAQriUn84E8SYuGmtAGmW8YVwqUyoUYgQ@mail.gmail.com>
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On Wed, 2023-08-02 at 17:00 -0300, Leonardo Bras Soares Passos wrote:
> On Thu, May 25, 2023 at 7:07=E2=80=AFAM Guo Ren <guoren@kernel.org> wrote=
:
> >=20
> > On Thu, May 25, 2023 at 5:31=E2=80=AFPM Leonardo Bras Soares Passos
> > <leobras@redhat.com> wrote:
> > >=20
> > > Friendly ping?
> > >=20
> > > On Wed, Apr 19, 2023 at 3:25=E2=80=AFAM Leonardo Bras <leobras@redhat=
.com> wrote:
> > > >=20
> > > > Some functions use mostly the same asm for 32-bit and 64-bit versio=
ns.
> > > >=20
> > > > Make a macro that is generic enough and avoid code duplication.
> > > >=20
> > > > Signed-off-by: Leonardo Bras <leobras@redhat.com>
> > > > ---
> > > >  arch/riscv/include/asm/atomic.h | 164 +++++++++++++++-------------=
----
> > > >  1 file changed, 76 insertions(+), 88 deletions(-)
> > > >=20
> > > > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/a=
sm/atomic.h
> > > > index 0dfe9d857a762..85eb2edbc8219 100644
> > > > --- a/arch/riscv/include/asm/atomic.h
> > > > +++ b/arch/riscv/include/asm/atomic.h
> > > > @@ -196,22 +196,28 @@ ATOMIC_OPS(xor, xor, i)
> > > >  #undef ATOMIC_FETCH_OP
> > > >  #undef ATOMIC_OP_RETURN
> > > >=20
> > > > +#define _arch_atomic_fetch_add_unless(_prev, _rc, counter, _a, _u,=
 sfx)        \
> > > > +({                                                                =
     \
> > > > +       __asm__ __volatile__ (                                     =
     \
> > > > +               "0:     lr." sfx "     %[p],  %[c]\n"              =
     \
> > > > +               "       beq            %[p],  %[u], 1f\n"          =
     \
> > > > +               "       add            %[rc], %[p], %[a]\n"        =
     \
> > > > +               "       sc." sfx ".rl  %[rc], %[rc], %[c]\n"       =
     \
> > > > +               "       bnez           %[rc], 0b\n"                =
     \
> > > > +               "       fence          rw, rw\n"                   =
     \
> > > > +               "1:\n"                                             =
     \
> > > > +               : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (c=
ounter)  \
> > > > +               : [a]"r" (_a), [u]"r" (_u)                         =
     \
> > > > +               : "memory");                                       =
     \
> > > > +})
> > > > +
> > > >  /* This is required to provide a full barrier on success. */
> > > >  static __always_inline int arch_atomic_fetch_add_unless(atomic_t *=
v, int a, int u)
> > > >  {
> > > >         int prev, rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.w     %[p],  %[c]\n"
> > > > -               "       beq      %[p],  %[u], 1f\n"
> > > > -               "       add      %[rc], %[p], %[a]\n"
> > > > -               "       sc.w.rl  %[rc], %[rc], %[c]\n"
> > > > -               "       bnez     %[rc], 0b\n"
> > > > -               "       fence    rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               : [a]"r" (a), [u]"r" (u)
> > > > -               : "memory");
> > > > +       _arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "=
w");
> > > > +
> > > >         return prev;
> > > >  }
> > > >  #define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
> > > > @@ -222,17 +228,8 @@ static __always_inline s64 arch_atomic64_fetch=
_add_unless(atomic64_t *v, s64 a,
> > > >         s64 prev;
> > > >         long rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.d     %[p],  %[c]\n"
> > > > -               "       beq      %[p],  %[u], 1f\n"
> > > > -               "       add      %[rc], %[p], %[a]\n"
> > > > -               "       sc.d.rl  %[rc], %[rc], %[c]\n"
> > > > -               "       bnez     %[rc], 0b\n"
> > > > -               "       fence    rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               : [a]"r" (a), [u]"r" (u)
> > > > -               : "memory");
> > > > +       _arch_atomic_fetch_add_unless(prev, rc, v->counter, a, u, "=
d");
> > > > +
> > > >         return prev;
> > > >  }
> > > >  #define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unl=
ess
> > > > @@ -310,61 +307,79 @@ ATOMIC_OPS()
> > > >  #undef ATOMIC_OPS
> > > >  #undef ATOMIC_OP
> > > >=20
> > > > +#define _arch_atomic_inc_unless_negative(_prev, _rc, counter, sfx)=
     \
> > > > +({                                                                =
     \
> > > > +       __asm__ __volatile__ (                                     =
     \
> > > > +               "0:     lr." sfx "      %[p],  %[c]\n"             =
     \
> > > > +               "       bltz            %[p],  1f\n"               =
     \
> > > > +               "       addi            %[rc], %[p], 1\n"          =
     \
> > > > +               "       sc." sfx ".rl   %[rc], %[rc], %[c]\n"      =
     \
> > > > +               "       bnez            %[rc], 0b\n"               =
     \
> > > > +               "       fence           rw, rw\n"                  =
     \
> > > > +               "1:\n"                                             =
     \
> > > > +               : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (c=
ounter)  \
> > > > +               :                                                  =
     \
> > > > +               : "memory");                                       =
     \
> > > > +})
> > > > +
> > > >  static __always_inline bool arch_atomic_inc_unless_negative(atomic=
_t *v)
> > > >  {
> > > >         int prev, rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.w      %[p],  %[c]\n"
> > > > -               "       bltz      %[p],  1f\n"
> > > > -               "       addi      %[rc], %[p], 1\n"
> > > > -               "       sc.w.rl   %[rc], %[rc], %[c]\n"
> > > > -               "       bnez      %[rc], 0b\n"
> > > > -               "       fence     rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               :
> > > > -               : "memory");
> > > > +       _arch_atomic_inc_unless_negative(prev, rc, v->counter, "w")=
;
> > > > +
> > > >         return !(prev < 0);
> > > >  }
> > > >=20
> > > >  #define arch_atomic_inc_unless_negative arch_atomic_inc_unless_neg=
ative
> > > >=20
> > > > +#define _arch_atomic_dec_unless_positive(_prev, _rc, counter, sfx)=
     \
> > > > +({                                                                =
     \
> > > > +       __asm__ __volatile__ (                                     =
     \
> > > > +               "0:     lr." sfx "      %[p],  %[c]\n"             =
     \
> > > > +               "       bgtz            %[p],  1f\n"               =
     \
> > > > +               "       addi            %[rc], %[p], -1\n"         =
     \
> > > > +               "       sc." sfx ".rl   %[rc], %[rc], %[c]\n"      =
     \
> > > > +               "       bnez            %[rc], 0b\n"               =
     \
> > > > +               "       fence           rw, rw\n"                  =
     \
> > > > +               "1:\n"                                             =
     \
> > > > +               : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (c=
ounter)  \
> > > > +               :                                                  =
     \
> > > > +               : "memory");                                       =
     \
> > > > +})
> > > > +
> > > >  static __always_inline bool arch_atomic_dec_unless_positive(atomic=
_t *v)
> > > >  {
> > > >         int prev, rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.w      %[p],  %[c]\n"
> > > > -               "       bgtz      %[p],  1f\n"
> > > > -               "       addi      %[rc], %[p], -1\n"
> > > > -               "       sc.w.rl   %[rc], %[rc], %[c]\n"
> > > > -               "       bnez      %[rc], 0b\n"
> > > > -               "       fence     rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               :
> > > > -               : "memory");
> > > > +       _arch_atomic_dec_unless_positive(prev, rc, v->counter, "w")=
;
> > > > +
> > > >         return !(prev > 0);
> > > >  }
> > > >=20
> > > >  #define arch_atomic_dec_unless_positive arch_atomic_dec_unless_pos=
itive
> > > >=20
> > > > +#define _arch_atomic_dec_if_positive(_prev, _rc, counter, sfx)    =
     \
> > > > +({                                                                =
     \
> > > > +       __asm__ __volatile__ (                                     =
     \
> > > > +               "0:     lr." sfx "     %[p],  %[c]\n"              =
     \
> > > > +               "       addi           %[rc], %[p], -1\n"          =
     \
> > > > +               "       bltz           %[rc], 1f\n"                =
     \
> > > > +               "       sc." sfx ".rl  %[rc], %[rc], %[c]\n"       =
     \
> > > > +               "       bnez           %[rc], 0b\n"                =
     \
> > > > +               "       fence          rw, rw\n"                   =
     \
> > > > +               "1:\n"                                             =
     \
> > > > +               : [p]"=3D&r" (_prev), [rc]"=3D&r" (_rc), [c]"+A" (c=
ounter)  \
> > > > +               :                                                  =
     \
> > > > +               : "memory");                                       =
     \
> > > > +})
> > > > +
> > > >  static __always_inline int arch_atomic_dec_if_positive(atomic_t *v=
)
> > > >  {
> > > >         int prev, rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.w     %[p],  %[c]\n"
> > > > -               "       addi     %[rc], %[p], -1\n"
> > > > -               "       bltz     %[rc], 1f\n"
> > > > -               "       sc.w.rl  %[rc], %[rc], %[c]\n"
> > > > -               "       bnez     %[rc], 0b\n"
> > > > -               "       fence    rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               :
> > > > -               : "memory");
> > > > +       _arch_atomic_dec_if_positive(prev, rc, v->counter, "w");
> > > > +
> > > >         return prev - 1;
> > > >  }
> > > >=20
> > > > @@ -376,17 +391,8 @@ static __always_inline bool arch_atomic64_inc_=
unless_negative(atomic64_t *v)
> > > >         s64 prev;
> > > >         long rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.d      %[p],  %[c]\n"
> > > > -               "       bltz      %[p],  1f\n"
> > > > -               "       addi      %[rc], %[p], 1\n"
> > > > -               "       sc.d.rl   %[rc], %[rc], %[c]\n"
> > > > -               "       bnez      %[rc], 0b\n"
> > > > -               "       fence     rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               :
> > > > -               : "memory");
> > > > +       _arch_atomic_inc_unless_negative(prev, rc, v->counter, "d")=
;
> > > > +
> > > >         return !(prev < 0);
> > > >  }
> > > >=20
> > > > @@ -397,17 +403,8 @@ static __always_inline bool arch_atomic64_dec_=
unless_positive(atomic64_t *v)
> > > >         s64 prev;
> > > >         long rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.d      %[p],  %[c]\n"
> > > > -               "       bgtz      %[p],  1f\n"
> > > > -               "       addi      %[rc], %[p], -1\n"
> > > > -               "       sc.d.rl   %[rc], %[rc], %[c]\n"
> > > > -               "       bnez      %[rc], 0b\n"
> > > > -               "       fence     rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               :
> > > > -               : "memory");
> > > > +       _arch_atomic_dec_unless_positive(prev, rc, v->counter, "d")=
;
> > > > +
> > > >         return !(prev > 0);
> > > >  }
> > > >=20
> > > > @@ -418,17 +415,8 @@ static __always_inline s64 arch_atomic64_dec_i=
f_positive(atomic64_t *v)
> > > >         s64 prev;
> > > >         long rc;
> > > >=20
> > > > -       __asm__ __volatile__ (
> > > > -               "0:     lr.d     %[p],  %[c]\n"
> > > > -               "       addi      %[rc], %[p], -1\n"
> > > > -               "       bltz     %[rc], 1f\n"
> > > > -               "       sc.d.rl  %[rc], %[rc], %[c]\n"
> > > > -               "       bnez     %[rc], 0b\n"
> > > > -               "       fence    rw, rw\n"
> > > > -               "1:\n"
> > > > -               : [p]"=3D&r" (prev), [rc]"=3D&r" (rc), [c]"+A" (v->=
counter)
> > > > -               :
> > > > -               : "memory");
> > > > +       _arch_atomic_dec_if_positive(prev, rc, v->counter, "d");
> > > > +
> > > >         return prev - 1;
> > > >  }
> > > >=20
> > > > --
> > > > 2.40.0
> > > >=20
> > >=20
> > A safe cleanup, no problem found.
> >=20
> > Reviewed-by: Guo Ren <guoren@kernel.org>
> >=20
> >=20
>=20
> Hello Palmer,
>=20
> Any improvements you suggest for this patch?
>=20
> Best regards,
> Leonardo Bras

Superseded by v2:
https://patchwork.kernel.org/project/linux-riscv/list/?series=3D772422&stat=
e=3D%2A&archive=3Dboth

Leo