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From:   Jernej =?utf-8?B?xaBrcmFiZWM=?= <jernej.skrabec@gmail.com>
To:     Andre Przywara <andre.przywara@arm.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Chen-Yu Tsai <wens@csie.org>,
        Samuel Holland <samuel@sholland.org>,
        Icenowy Zheng <uwu@icenowy.me>,
        Piotr Oniszczuk <piotr.oniszczuk@gmail.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/3] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board
 support
Date:   Sat, 05 Aug 2023 08:32:34 +0200
Message-ID: <2691070.mvXUDI8C0e@jernej-laptop>
In-Reply-To: <20230804235827.3f32fa8f@slackpad.lan>
References: <20230804170856.1237202-1-andre.przywara@arm.com>
 <4500165.LvFx2qVVIh@jernej-laptop> <20230804235827.3f32fa8f@slackpad.lan>
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Dne sobota, 05. avgust 2023 ob 00:58:27 CEST je Andre Przywara napisal(a):
> On Fri, 04 Aug 2023 21:05:36 +0200
> Jernej =C5=A0krabec <jernej.skrabec@gmail.com> wrote:
>=20
> Hi Jernej,
>=20
> > Dne petek, 04. avgust 2023 ob 19:08:56 CEST je Andre Przywara napisal(a=
):
> > > The OrangePi Zero 3 is a development board based on the Allwinner H618
> > > SoC,
> > > which seems to be just an H616 with more L2 cache. The board itself i=
s a
> > > slightly updated version of the Orange Pi Zero 2. It features:
> > > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> > > - 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2)
> > > - AXP313a PMIC (more capable AXP305 on the Zero2)
> > > - Raspberry-Pi-1 compatible GPIO header
> > > - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
> > > - 1 USB 2.0 host port
> > > - 1 USB 2.0 type C port (power supply + OTG)
> > > - MicroSD slot
> > > - on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2)
> > > - 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero=
2)
> > > - micro-HDMI port
> > > - (yet) unsupported Allwinner WiFi/BT chip
> > >=20
> > > Add the devicetree file describing the currently supported features,
> > > namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at
> > > the moment, though the basic functionality works.
> > >=20
> > > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > > ---
> > >=20
> > >  arch/arm64/boot/dts/allwinner/Makefile        |  1 +
> > >  .../allwinner/sun50i-h618-orangepi-zero3.dts  | 94 +++++++++++++++++=
++
> > >  2 files changed, 95 insertions(+)
> > >  create mode 100644
> > >=20
> > > arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
> > >=20
> > > diff --git a/arch/arm64/boot/dts/allwinner/Makefile
> > > b/arch/arm64/boot/dts/allwinner/Makefile index
> > > 6a96494a2e0a3..3b0ad54062381
> > > 100644
> > > --- a/arch/arm64/boot/dts/allwinner/Makefile
> > > +++ b/arch/arm64/boot/dts/allwinner/Makefile
> > > @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6.d=
tb
> > >=20
> > >  dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h6-tanix-tx6-mini.dtb
> > >  dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-orangepi-zero2.dtb
> > >  dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h616-x96-mate.dtb
> > >=20
> > > +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-orangepi-zero3.dtb
> > > diff --git
> > > a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
> > > b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts new fi=
le
> > > mode 100644
> > > index 0000000000000..96a6851728111
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
> > > @@ -0,0 +1,94 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > > +/*
> > > + * Copyright (C) 2023 Arm Ltd.
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "sun50i-h616-orangepi-zero.dtsi"
> > > +
> > > +/ {
> > > +	model =3D "OrangePi Zero3";
> > > +	compatible =3D "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
> > > +};
> > > +
> > > +&emac0 {
> > > +	phy-supply =3D <&reg_dldo1>;
> > > +};
> > > +
> > > +&ext_rgmii_phy {
> > > +	motorcomm,clk-out-frequency-hz =3D <125000000>;
> > > +};
> > > +
> > > +&mmc0 {
> > > +	/*
> > > +	 * The schematic shows the card detect pin wired up to PF6, via an
> > > +	 * inverter, but it just doesn't work.
> > > +	 */
> > > +	broken-cd;
> > > +	vmmc-supply =3D <&reg_dldo1>;
> > > +};
> > > +
> > > +&r_i2c {
> > > +	status =3D "okay";
> > > +
> > > +	axp313: pmic@36 {
> > > +		compatible =3D "x-powers,axp313a";
> > > +		reg =3D <0x36>;
> > > +		#interrupt-cells =3D <1>;
> > > +		interrupt-controller;
> > > +		interrupt-parent =3D <&pio>;
> > > +		interrupts =3D <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9=20
*/
> > > +
> > > +		vin1-supply =3D <&reg_vcc5v>;
> > > +		vin2-supply =3D <&reg_vcc5v>;
> > > +		vin3-supply =3D <&reg_vcc5v>;
> > > +
> > > +		regulators {
> > > +			/* Supplies VCC-PLL, so needs to be always
> >=20
> > on. */
> >=20
> > > +			reg_aldo1: aldo1 {
> > > +				regulator-always-on;
> > > +				regulator-min-microvolt =3D
> >=20
> > <1800000>;
> >=20
> > > +				regulator-max-microvolt =3D
> >=20
> > <1800000>;
> >=20
> > > +				regulator-name =3D "vcc1v8";
> > > +			};
> > > +
> > > +			/* Supplies VCC-IO, so needs to be always=20
on.
> >=20
> > */
> >=20
> > > +			reg_dldo1: dldo1 {
> > > +				regulator-always-on;
> > > +				regulator-min-microvolt =3D
> >=20
> > <3300000>;
> >=20
> > > +				regulator-max-microvolt =3D
> >=20
> > <3300000>;
> >=20
> > > +				regulator-name =3D "vcc3v3";
> > > +			};
> > > +
> > > +			reg_dcdc1: dcdc1 {
> > > +				regulator-always-on;
> > > +				regulator-min-microvolt =3D
> >=20
> > <810000>;
> >=20
> > > +				regulator-max-microvolt =3D
> >=20
> > <990000>;
> >=20
> > > +				regulator-name =3D "vdd-gpu-sys";
> > > +			};
> >=20
> > Is it safe to change sys voltage when system is running?
>=20
> I don't know. All I know is that the H616 datasheet lists VDD_SYS as
> having the exact same range as VDD_GPU, and that is does not give a
> "typical" voltage value. As this DT stands at the moment, this doesn't
> really matter, since nothing will change DCDC1.
>=20
> I see that the Orange Pi Zero 2 (with a "proper" PMIC) also ties SYS and
> GPU together, so it's not just because of the few rails of the AXP313.
>=20
> I'd say we will figure that out once we start experimenting with GPU
> DVFS, but meanwhile nothing references DCDC1, so it will just stay put
> at the AXP313's 0.9V reset value.
>=20
> Does that make sense?

Yeah, I'm fine with it.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

>=20
> Cheers,
> Andre
>=20
> > > +
> > > +			reg_dcdc2: dcdc2 {
> > > +				regulator-always-on;
> > > +				regulator-min-microvolt =3D
> >=20
> > <810000>;
> >=20
> > > +				regulator-max-microvolt =3D
> >=20
> > <1100000>;
> >=20
> > > +				regulator-name =3D "vdd-cpu";
> > > +			};
> > > +
> > > +			reg_dcdc3: dcdc3 {
> > > +				regulator-always-on;
> > > +				regulator-min-microvolt =3D
> >=20
> > <1100000>;
> >=20
> > > +				regulator-max-microvolt =3D
> >=20
> > <1100000>;
> >=20
> > > +				regulator-name =3D "vdd-dram";
> > > +			};
> > > +		};
> > > +	};
> > > +};
> > > +
> > > +&pio {
> > > +	vcc-pc-supply =3D <&reg_dldo1>;
> > > +	vcc-pf-supply =3D <&reg_dldo1>;
> > > +	vcc-pg-supply =3D <&reg_aldo1>;
> > > +	vcc-ph-supply =3D <&reg_dldo1>;
> > > +	vcc-pi-supply =3D <&reg_dldo1>;
> > > +};