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Date:   Sun, 6 Aug 2023 12:53:38 -0500
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Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
 manager
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To:     "Rabara, Niravkumar L" <niravkumar.l.rabara@intel.com>,
        Conor Dooley <conor.dooley@microchip.com>
Cc:     "Ng, Adrian Ho Yin" <adrian.ho.yin.ng@intel.com>,
        "andrew@lunn.ch" <andrew@lunn.ch>,
        "conor+dt@kernel.org" <conor+dt@kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Turquette, Mike" <mturquette@baylibre.com>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "richardcochran@gmail.com" <richardcochran@gmail.com>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        "wen.ping.teh@intel.com" <wen.ping.teh@intel.com>
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From:   Dinh Nguyen <dinguyen@kernel.org>
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On 8/2/23 02:14, Rabara, Niravkumar L wrote:
> 
> 
>> -----Original Message-----
>> From: Conor Dooley <conor.dooley@microchip.com>
>> Sent: Wednesday, 2 August, 2023 3:02 PM
>> To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>
>> Cc: Ng, Adrian Ho Yin <adrian.ho.yin.ng@intel.com>; andrew@lunn.ch;
>> conor+dt@kernel.org; devicetree@vger.kernel.org; dinguyen@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; linux-clk@vger.kernel.org; linux-
>> kernel@vger.kernel.org; Turquette, Mike <mturquette@baylibre.com>;
>> netdev@vger.kernel.org; p.zabel@pengutronix.de;
>> richardcochran@gmail.com; robh+dt@kernel.org; sboyd@kernel.org;
>> wen.ping.teh@intel.com
>> Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
>> manager
>>
>> On Wed, Aug 02, 2023 at 10:58:42AM +0800, niravkumar.l.rabara@intel.com
>> wrote:
>>> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>>>
>>> Add clock ID definitions for Intel Agilex5 SoCFPGA.
>>> The registers in Agilex5 handling the clock is named as clock manager.
>>>
>>> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
>>> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
>>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>>
>> Damn, I was too late - you already sent a v3 :/
>>
>> However, there only seems to be a v3 of this one patch and it was sent in
>> reply to the v2 series? The normal thing to do is resend the entire series, not
>> just one patch, as a new thread. Not using a new thread may make it harder
>> to apply & will also bury the email in people's mailboxes that use things like
>> mutt. A single patch as a reply is also confusing, as the rest of the v3 looks like
>> it is missing!
>>
>> Thanks,
>> Conor.
> 
> Sorry I made a mistake.
> Should I send out entire series with PATCH v3 subject? Or should I wait for review comment on remaining patches and then send entire series with rework and  subject prefix PATCH v3?
> 

No need to send out a V3. I've applied patches 1-3 and 5. Will give a 
little more time for the clk patch.

Dinh