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Message-ID: <3a2d1880-10aa-ac19-24e1-b2f697bc1a73@ti.com>
Date:   Mon, 7 Aug 2023 10:01:16 +0530
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Subject: Re: [PATCH 2/3] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add
 bootph-pre-ram property for SPL nodes
To:     Apurva Nandan <a-nandan@ti.com>, Nishanth Menon <nm@ti.com>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Tero Kristo <kristo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Hari Nagalla <hnagalla@ti.com>
References: <20230806164838.18088-1-a-nandan@ti.com>
 <20230806164838.18088-3-a-nandan@ti.com>
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From:   "Kumar, Udit" <u-kumar1@ti.com>
In-Reply-To: <20230806164838.18088-3-a-nandan@ti.com>
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Hi Apurva

On 8/6/2023 10:18 PM, Apurva Nandan wrote:
> Add bootph-pre-ram property for all the nodes used in SPL stage,
> for syncing it later to u-boot j784s4 dts.
>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> index 740ee794d7b9..57bf0261c343 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
> @@ -6,7 +6,9 @@
>    */
>   
>   &cbass_mcu_wakeup {
> +	bootph-pre-ram;
>   	sms: system-controller@44083000 {
> +		bootph-pre-ram;
>   		compatible = "ti,k2g-sci";
>   		ti,host-id = <12>;
>   
> @@ -19,22 +21,26 @@ sms: system-controller@44083000 {
>   		reg = <0x00 0x44083000 0x00 0x1000>;
>   
>   		k3_pds: power-controller {
> +			bootph-pre-ram;
>   			compatible = "ti,sci-pm-domain";
>   			#power-domain-cells = <2>;
>   		};
>   
>   		k3_clks: clock-controller {
> +			bootph-pre-ram;
>   			compatible = "ti,k2g-sci-clk";
>   			#clock-cells = <2>;
>   		};
>   
>   		k3_reset: reset-controller {
> +			bootph-pre-ram;
>   			compatible = "ti,sci-reset";
>   			#reset-cells = <2>;
>   		};
>   	};
>   
>   	chipid@43000014 {
> +		bootph-pre-ram;
>   		compatible = "ti,am654-chipid";
>   		reg = <0x00 0x43000014 0x00 0x4>;
>   	};
> @@ -442,6 +448,7 @@ mcu_spi2: spi@40320000 {
>   	};


mcu_timer0: timer@40400000 should be part of your list.

>   
>   	mcu_navss: bus@28380000 {
> +		bootph-pre-ram;
>   		compatible = "simple-bus";
>   		#address-cells = <2>;
>   		#size-cells = <2>;
> @@ -451,6 +458,7 @@ mcu_navss: bus@28380000 {
>   		dma-ranges;
>   
>   		mcu_ringacc: ringacc@2b800000 {
> +			bootph-pre-ram;
>   			compatible = "ti,am654-navss-ringacc";
>   			reg = <0x00 0x2b800000 0x00 0x400000>,
>   			      <0x00 0x2b000000 0x00 0x400000>,
> @@ -465,6 +473,7 @@ mcu_ringacc: ringacc@2b800000 {
>   		};
>   
>   		mcu_udmap: dma-controller@285c0000 {
> +			bootph-pre-ram;
>   			compatible = "ti,j721e-navss-mcu-udmap";
>   			reg = <0x00 0x285c0000 0x00 0x100>,
>   			      <0x00 0x2a800000 0x00 0x40000>,