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Message-ID: <6c1a4b77-996e-9274-bece-84fe42d6099a@starfivetech.com>
Date:   Mon, 7 Aug 2023 14:54:50 +0800
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Subject: Re: [PATCH v2 3/4] dt-bindings: PCI: Add StarFive JH7110 PCIe
 controller
Content-Language: en-US
To:     Conor Dooley <conor.dooley@microchip.com>
CC:     =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Daire McNamara <daire.mcnamara@microchip.com>,
        Conor Dooley <conor@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-pci@vger.kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Mason Huo <mason.huo@starfivetech.com>,
        Leyfoon Tan <leyfoon.tan@starfivetech.com>,
        Kevin Xie <kevin.xie@starfivetech.com>
References: <20230727103949.26149-1-minda.chen@starfivetech.com>
 <20230727103949.26149-4-minda.chen@starfivetech.com>
 <20230804-irregular-distrust-c5d46afe3d9c@wendy>
From:   Minda Chen <minda.chen@starfivetech.com>
In-Reply-To: <20230804-irregular-distrust-c5d46afe3d9c@wendy>
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On 2023/8/4 15:10, Conor Dooley wrote:
> On Thu, Jul 27, 2023 at 06:39:48PM +0800, Minda Chen wrote:
>> Add StarFive JH7110 SoC PCIe controller dt-bindings.
>> JH7110 using PLDA XpressRICH PCIe host controller IP.
>> 
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  .../bindings/pci/starfive,jh7110-pcie.yaml    | 133 ++++++++++++++++++
>>  1 file changed, 133 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>> new file mode 100644
>> index 000000000000..9273e029fb20
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>> @@ -0,0 +1,133 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 PCIe host controller
>> +
>> +maintainers:
>> +  - Kevin Xie <kevin.xie@starfivetech.com>
>> +
>> +allOf:
>> +  - $ref: /schemas/pci/pci-bus.yaml#
>> +  - $ref: plda,xpressrich3-axi-common.yaml#
>> +  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
>> +  - $ref: /schemas/gpio/gpio-consumer-common.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: starfive,jh7110-pcie
>> +
>> +  clocks:
>> +    items:
>> +      - description: NOC bus clock
>> +      - description: Transport layer clock
>> +      - description: AXI MST0 clock
>> +      - description: APB clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: noc
>> +      - const: tl
>> +      - const: axi_mst0
>> +      - const: apb
>> +
>> +  resets:
>> +    items:
>> +      - description: AXI MST0 reset
>> +      - description: AXI SLAVE0 reset
>> +      - description: AXI SLAVE reset
>> +      - description: PCIE BRIDGE reset
>> +      - description: PCIE CORE reset
>> +      - description: PCIE APB reset
>> +
>> +  reset-names:
>> +    items:
>> +      - const: mst0
>> +      - const: slv0
>> +      - const: slv
>> +      - const: brg
>> +      - const: core
>> +      - const: apb
>> +
>> +  starfive,stg-syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      - items:
>> +          - description: phandle to System Register Controller stg_syscon node.
>> +          - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>> +          - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>> +          - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>> +          - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
>> +    description:
>> +      The phandle to System Register Controller syscon node and the offset
>> +      of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
>> +      for PCIe.
> 
> These property names tie them closely with naming on the jh7110, but
> there's little value in specifying all of these offsets when you have
> one implementation where they are all fixed.
Yes, the offset value is tied to SoC. 
> Do you know what the jh81xx stuff is going to do yet w.r.t. PCI and if
> so, how could you reuse this property?
I do not participate in jh8100. But I heard sys-syscon is exist in 81xx.
But I think stg-syscon and sys-syscon  can be move to a common dt-binding doc.
Bot 71x0 and 81x0 driver can use this. 
> Particularly, saying "register 0" seems unlikely to transfer well
> between SoCs.
> I'd be inclined to drop the offsets entirely & rely on match data to
> provide them if needed in the future.
That's ok. The dts can change to starfive,stg-syscon = <&stg_syscon>;
I will try to move the offset to driver match data.
>> +
>> +  phys:
>> +    description:
>> +      Specified PHY is attached to PCIe controller.
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - resets
>> +  - starfive,stg-syscon
>> +  - "#interrupt-cells"
>> +  - interrupt-map-mask
>> +  - interrupt-map
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/gpio/gpio.h>
>> +    soc {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +
>> +        pcie0: pcie@2b000000 {
> 
> nit: you don't need labels in examples if they are not referenced
> anywhere.
> 
> Otherwise, this looks good to me.
> 
> Thanks,
> Conor.
> 
ok, thanks.
>> +            compatible = "starfive,jh7110-pcie";
>> +            reg = <0x9 0x40000000 0x0 0x10000000>,
>> +                  <0x0 0x2b000000 0x0 0x1000000>;
>> +            reg-names = "cfg", "apb";
>> +            #address-cells = <3>;
>> +            #size-cells = <2>;
>> +            #interrupt-cells = <1>;
>> +            device_type = "pci";
>> +            ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
>> +                     <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
>> +            starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
>> +            bus-range = <0x0 0xff>;
>> +            interrupt-parent = <&plic>;
>> +            interrupts = <56>;
>> +            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
>> +            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
>> +                            <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
>> +                            <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
>> +                            <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
>> +            msi-parent = <&pcie0>;
>> +            msi-controller;
>> +            clocks = <&syscrg 86>,
>> +                     <&stgcrg 10>,
>> +                     <&stgcrg 8>,
>> +                     <&stgcrg 9>;
>> +            clock-names = "noc", "tl", "axi_mst0", "apb";
>> +            resets = <&stgcrg 11>,
>> +                     <&stgcrg 12>,
>> +                     <&stgcrg 13>,
>> +                     <&stgcrg 14>,
>> +                     <&stgcrg 15>,
>> +                     <&stgcrg 16>;
>> +            reset-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
>> +            phys = <&pciephy0>;
>> +
>> +            pcie_intc0: interrupt-controller {
>> +                #address-cells = <0>;
>> +                #interrupt-cells = <1>;
>> +                interrupt-controller;
>> +            };
>> +        };
>> +    };
>> -- 
>> 2.17.1
>>