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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 81d58c51-388d-4253-9eb5-08db971fc46d X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Aug 2023 08:24:49.8026 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tpO/YW/0RheahC+IqqMQoq1dDdKYgBzQBQNsTz4nHYTa990RxFVejWN/v520ikbbMOGjWvhkjC8qbn3oKXvYcg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8541 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: [PATCH v2] clk: imx: composite-8m: fix clock pauses when set_rat= e > would be a no-op >=20 > Reconfiguring the clock divider to the exact same value is observed on an > i.MX8MN to often cause a longer than usual clock pause, probably because > the divider restarts counting whenever the register is rewritten. >=20 > This issue doesn't show up normally, because the clock framework will tak= e > care to not call set_rate when the clock rate is the same. > However, when we reconfigure an upstream clock, the common code will > call set_rate with the newly calculated rate on all children, e.g.: >=20 > - sai5 is running normally and divides Audio PLL out by 16. > - Audio PLL rate is increased by 32Hz (glitch-free kdiv change) > - rates for children are recalculated and rates are set recursively > - imx8m_clk_composite_divider_set_rate(sai5) is called with > 32/16 =3D 2Hz more > - imx8m_clk_composite_divider_set_rate computes same divider as before > - divider register is written, so it restarts counting from zero and > MCLK is briefly paused, so instead of e.g. 40ns, MCLK is low for 120n= s. >=20 > Some external clock consumers can be upset by such unexpected clock > pauses, so let's make sure we only rewrite the divider value when the val= ue > to be written is actually different. >=20 > Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") > Signed-off-by: Ahmad Fatoum Reviewed-by: Peng Fan Regards, Peng.