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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 7 Aug 2023 12:39:18 -0400
Message-ID: <CADnq5_Oe8gktj8EMc3dRkbd=LojOiCh8W1MoEghOJnRA+eRW8Q@mail.gmail.com>
Subject: Re: [PATCH] drm/amd: Clean up errors in smu7_hwmgr.c
To:     Ran Sun <sunran001@208suo.com>
Cc:     alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch,
        dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
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Applied.  Thanks!

On Tue, Aug 1, 2023 at 5:00=E2=80=AFAM Ran Sun <sunran001@208suo.com> wrote=
:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: that open brace { should be on the previous line
> ERROR: spaces required around that '=3D' (ctx:VxV)
> ERROR: spaces required around that '<' (ctx:VxV)
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>  .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 26 +++++++++----------
>  1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/driver=
s/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> index 1cb402264497..425859682fab 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
> @@ -83,15 +83,15 @@
>  #define PCIE_BUS_CLK                10000
>  #define TCLK                        (PCIE_BUS_CLK / 10)
>
> -static struct profile_mode_setting smu7_profiling[7] =3D
> -                                       {{0, 0, 0, 0, 0, 0, 0, 0},
> +static struct profile_mode_setting smu7_profiling[7] =3D {
> +                                        {0, 0, 0, 0, 0, 0, 0, 0},
>                                          {1, 0, 100, 30, 1, 0, 100, 10},
>                                          {1, 10, 0, 30, 0, 0, 0, 0},
>                                          {0, 0, 0, 0, 1, 10, 16, 31},
>                                          {1, 0, 11, 50, 1, 0, 100, 10},
>                                          {1, 0, 5, 30, 0, 0, 0, 0},
>                                          {0, 0, 0, 0, 0, 0, 0, 0},
> -                                       };
> +};
>
>  #define PPSMC_MSG_SetVBITimeout_VEGAM    ((uint16_t) 0x310)
>
> @@ -950,7 +950,7 @@ static int smu7_odn_initial_default_setting(struct pp=
_hwmgr *hwmgr)
>         odn_table->odn_core_clock_dpm_levels.num_of_pl =3D
>                                                 data->golden_dpm_table.sc=
lk_table.count;
>         entries =3D odn_table->odn_core_clock_dpm_levels.entries;
> -       for (i=3D0; i<data->golden_dpm_table.sclk_table.count; i++) {
> +       for (i =3D 0; i < data->golden_dpm_table.sclk_table.count; i++) {
>                 entries[i].clock =3D data->golden_dpm_table.sclk_table.dp=
m_levels[i].value;
>                 entries[i].enabled =3D true;
>                 entries[i].vddc =3D dep_sclk_table->entries[i].vddc;
> @@ -962,7 +962,7 @@ static int smu7_odn_initial_default_setting(struct pp=
_hwmgr *hwmgr)
>         odn_table->odn_memory_clock_dpm_levels.num_of_pl =3D
>                                                 data->golden_dpm_table.mc=
lk_table.count;
>         entries =3D odn_table->odn_memory_clock_dpm_levels.entries;
> -       for (i=3D0; i<data->golden_dpm_table.mclk_table.count; i++) {
> +       for (i =3D 0; i < data->golden_dpm_table.mclk_table.count; i++) {
>                 entries[i].clock =3D data->golden_dpm_table.mclk_table.dp=
m_levels[i].value;
>                 entries[i].enabled =3D true;
>                 entries[i].vddc =3D dep_mclk_table->entries[i].vddc;
> @@ -1813,13 +1813,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmg=
r *hwmgr)
>         data->static_screen_threshold =3D SMU7_STATICSCREENTHRESHOLD_DFLT=
;
>         data->static_screen_threshold_unit =3D SMU7_STATICSCREENTHRESHOLD=
UNIT_DFLT;
>         data->voting_rights_clients[0] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT0=
;
> -       data->voting_rights_clients[1]=3D SMU7_VOTINGRIGHTSCLIENTS_DFLT1;
> +       data->voting_rights_clients[1] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT1=
;
>         data->voting_rights_clients[2] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT2=
;
> -       data->voting_rights_clients[3]=3D SMU7_VOTINGRIGHTSCLIENTS_DFLT3;
> -       data->voting_rights_clients[4]=3D SMU7_VOTINGRIGHTSCLIENTS_DFLT4;
> -       data->voting_rights_clients[5]=3D SMU7_VOTINGRIGHTSCLIENTS_DFLT5;
> -       data->voting_rights_clients[6]=3D SMU7_VOTINGRIGHTSCLIENTS_DFLT6;
> -       data->voting_rights_clients[7]=3D SMU7_VOTINGRIGHTSCLIENTS_DFLT7;
> +       data->voting_rights_clients[3] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT3=
;
> +       data->voting_rights_clients[4] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT4=
;
> +       data->voting_rights_clients[5] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT5=
;
> +       data->voting_rights_clients[6] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT6=
;
> +       data->voting_rights_clients[7] =3D SMU7_VOTINGRIGHTSCLIENTS_DFLT7=
;
>
>         data->mclk_dpm_key_disabled =3D hwmgr->feature_mask & PP_MCLK_DPM=
_MASK ? false : true;
>         data->sclk_dpm_key_disabled =3D hwmgr->feature_mask & PP_SCLK_DPM=
_MASK ? false : true;
> @@ -2002,7 +2002,7 @@ static int smu7_calculate_ro_range(struct pp_hwmgr =
*hwmgr)
>         } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision=
) ||
>                    ASICID_IS_P31(adev->pdev->device, adev->pdev->revision=
)) {
>                 min =3D 900;
> -               max=3D 2100;
> +               max =3D 2100;
>         } else if (hwmgr->chip_id =3D=3D CHIP_POLARIS10) {
>                 if (adev->pdev->subsystem_vendor =3D=3D 0x106B) {
>                         min =3D 1000;
> @@ -4018,7 +4018,7 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr,=
 int idx,
>                 offset =3D data->soft_regs_start + smum_get_offsetof(hwmg=
r,
>                                                                 SMU_SoftR=
egisters,
>                                                                 (idx =3D=
=3D AMDGPU_PP_SENSOR_GPU_LOAD) ?
> -                                                               AverageGr=
aphicsActivity:
> +                                                               AverageGr=
aphicsActivity :
>                                                                 AverageMe=
moryActivity);
>
>                 activity_percent =3D cgs_read_ind_register(hwmgr->device,=
 CGS_IND_REG__SMC, offset);
> --
> 2.17.1
>