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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 7 Aug 2023 12:26:57 -0400
Message-ID: <CADnq5_OnifyV7Debd_GsGFA1yPkr454GLLb0d5Wsd00tg=V1aA@mail.gmail.com>
Subject: Re: [PATCH] drm/amd/pm: Clean up errors in smu10_hwmgr.c
To:     Ran Sun <sunran001@208suo.com>
Cc:     alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch,
        dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
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Applied.  Thanks!

On Mon, Jul 31, 2023 at 11:09=E2=80=AFPM Ran Sun <sunran001@208suo.com> wro=
te:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: spaces required around that '=3D' (ctx:VxW)
> ERROR: space required after that ',' (ctx:VxV)
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>  .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drive=
rs/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> index 86d6e88c7386..02ba68d7c654 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
> @@ -430,37 +430,37 @@ static int smu10_apply_state_adjust_rules(struct pp=
_hwmgr *hwmgr,
>  }
>
>  /* temporary hardcoded clock voltage breakdown tables */
> -static const DpmClock_t VddDcfClk[]=3D {
> +static const DpmClock_t VddDcfClk[] =3D {
>         { 300, 2600},
>         { 600, 3200},
>         { 600, 3600},
>  };
>
> -static const DpmClock_t VddSocClk[]=3D {
> +static const DpmClock_t VddSocClk[] =3D {
>         { 478, 2600},
>         { 722, 3200},
>         { 722, 3600},
>  };
>
> -static const DpmClock_t VddFClk[]=3D {
> +static const DpmClock_t VddFClk[] =3D {
>         { 400, 2600},
>         {1200, 3200},
>         {1200, 3600},
>  };
>
> -static const DpmClock_t VddDispClk[]=3D {
> +static const DpmClock_t VddDispClk[] =3D {
>         { 435, 2600},
>         { 661, 3200},
>         {1086, 3600},
>  };
>
> -static const DpmClock_t VddDppClk[]=3D {
> +static const DpmClock_t VddDppClk[] =3D {
>         { 435, 2600},
>         { 661, 3200},
>         { 661, 3600},
>  };
>
> -static const DpmClock_t VddPhyClk[]=3D {
> +static const DpmClock_t VddPhyClk[] =3D {
>         { 540, 2600},
>         { 810, 3200},
>         { 810, 3600},
> @@ -1358,7 +1358,7 @@ static int smu10_set_watermarks_for_clocks_ranges(s=
truct pp_hwmgr *hwmgr,
>         struct amdgpu_device *adev =3D hwmgr->adev;
>         int i;
>
> -       smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
> +       smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges)=
;
>
>         if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
>                 for (i =3D 0; i < NUM_WM_RANGES; i++)
> @@ -1461,7 +1461,7 @@ static int smu10_get_power_profile_mode(struct pp_h=
wmgr *hwmgr, char *buf)
>
>         phm_get_sysfs_buf(&buf, &size);
>
> -       size +=3D sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[=
0],
> +       size +=3D sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n", title=
[0],
>                         title[1], title[2], title[3], title[4], title[5])=
;
>
>         for (i =3D 0; i <=3D PP_SMC_POWER_PROFILE_COMPUTE; i++)
> --
> 2.17.1
>