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References: <20230801092821.7495-1-sunran001@208suo.com>
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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 7 Aug 2023 12:43:13 -0400
Message-ID: <CADnq5_NsAjYq=Fq8oSYYdfh+QB=TMgSjTZS+cLWWezunzzHU6Q@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu/powerplay: Clean up errors in vega20_hwmgr.c
To:     Ran Sun <sunran001@208suo.com>
Cc:     alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch,
        dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
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Applied.  Thanks!

On Tue, Aug 1, 2023 at 5:28=E2=80=AFAM Ran Sun <sunran001@208suo.com> wrote=
:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: code indent should use tabs where possible
> ERROR: space required before the open parenthesis '('
> ERROR: space prohibited before that close parenthesis ')'
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>  .../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c    | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/driv=
ers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> index 4e19ccbdb807..492ca33637d6 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
> @@ -1402,7 +1402,7 @@ static int vega20_od8_set_settings(
>                         "Failed to export over drive table!",
>                         return ret);
>
> -       switch(index) {
> +       switch (index) {
>         case OD8_SETTING_GFXCLK_FMIN:
>                 od_table.GfxclkFmin =3D (uint16_t)value;
>                 break;
> @@ -2360,7 +2360,7 @@ static int vega20_notify_smc_display_config_after_p=
s_adjustment(
>                 dpm_table->dpm_state.hard_min_level =3D min_clocks.memory=
Clock / 100;
>                 PP_ASSERT_WITH_CODE(!(ret =3D smum_send_msg_to_smc_with_p=
arameter(hwmgr,
>                                 PPSMC_MSG_SetHardMinByFreq,
> -                               (PPCLK_UCLK << 16 ) | dpm_table->dpm_stat=
e.hard_min_level,
> +                               (PPCLK_UCLK << 16) | dpm_table->dpm_state=
.hard_min_level,
>                                 NULL)),
>                                 "[SetHardMinFreq] Set hard min uclk faile=
d!",
>                                 return ret);
> @@ -3579,7 +3579,7 @@ static int vega20_set_uclk_to_highest_dpm_level(str=
uct pp_hwmgr *hwmgr,
>                 dpm_table->dpm_state.hard_min_level =3D dpm_table->dpm_le=
vels[dpm_table->count - 1].value;
>                 PP_ASSERT_WITH_CODE(!(ret =3D smum_send_msg_to_smc_with_p=
arameter(hwmgr,
>                                 PPSMC_MSG_SetHardMinByFreq,
> -                               (PPCLK_UCLK << 16 ) | dpm_table->dpm_stat=
e.hard_min_level,
> +                               (PPCLK_UCLK << 16) | dpm_table->dpm_state=
.hard_min_level,
>                                 NULL)),
>                                 "[SetUclkToHightestDpmLevel] Set hard min=
 uclk failed!",
>                                 return ret);
> @@ -3605,7 +3605,7 @@ static int vega20_set_fclk_to_highest_dpm_level(str=
uct pp_hwmgr *hwmgr)
>                 dpm_table->dpm_state.soft_min_level =3D dpm_table->dpm_le=
vels[dpm_table->count - 1].value;
>                 PP_ASSERT_WITH_CODE(!(ret =3D smum_send_msg_to_smc_with_p=
arameter(hwmgr,
>                                 PPSMC_MSG_SetSoftMinByFreq,
> -                               (PPCLK_FCLK << 16 ) | dpm_table->dpm_stat=
e.soft_min_level,
> +                               (PPCLK_FCLK << 16) | dpm_table->dpm_state=
.soft_min_level,
>                                 NULL)),
>                                 "[SetFclkToHightestDpmLevel] Set soft min=
 fclk failed!",
>                                 return ret);
> @@ -3727,8 +3727,8 @@ static int vega20_apply_clocks_adjust_rules(struct =
pp_hwmgr *hwmgr)
>         uint32_t i, latency;
>
>         disable_mclk_switching =3D ((1 < hwmgr->display_config->num_displ=
ay) &&
> -                           !hwmgr->display_config->multi_monitor_in_sync=
) ||
> -                            vblank_too_short;
> +                               !hwmgr->display_config->multi_monitor_in_=
sync) ||
> +                               vblank_too_short;
>         latency =3D hwmgr->display_config->dce_tolerable_mclk_in_active_l=
atency;
>
>         /* gfxclk */
> --
> 2.17.1
>