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References: <20230801061529.6269-1-sunran001@208suo.com>
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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 7 Aug 2023 12:34:02 -0400
Message-ID: <CADnq5_PizYO5faQR3AoGyZRq__sccQr9_6VuSqxv_DqKoM8SqQ@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu: Clean up errors in smu7_powertune.c
To:     Ran Sun <sunran001@208suo.com>
Cc:     alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch,
        dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
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Applied.  Thanks!

On Tue, Aug 1, 2023 at 2:15=E2=80=AFAM Ran Sun <sunran001@208suo.com> wrote=
:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: that open brace { should be on the previous line
> ERROR: space required after that ',' (ctx:VxV)
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>  .../gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c b/dr=
ivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
> index 21be23ec3c79..edab3ef09d33 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
> @@ -520,8 +520,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Pola=
ris12[] =3D {
>         {   0xFFFFFFFF  }
>  };
>
> -static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =3D
> -{
> +static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =3D =
{
>  /* ---------------------------------------------------------------------=
---------------------------------------------------------------------------=
---------------------------------
>   *      Offset                             Mask                         =
                       Shift                                               =
Value       Type
>   * ---------------------------------------------------------------------=
---------------------------------------------------------------------------=
---------------------------------
> @@ -646,7 +645,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Pola=
ris11_Kicker[] =3D
>         {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_=
STALL_CTRL_ENABLE_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIF=
T, 0x0001,     GPU_CONFIGREG_DIDT_IND },
>         {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_=
STALL_DELAY_HI_MASK,      DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, =
   0x0001,     GPU_CONFIGREG_DIDT_IND },
>         {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_=
STALL_DELAY_LO_MASK,      DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, =
   0x0001,     GPU_CONFIGREG_DIDT_IND },
> -       {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_=
HI_POWER_THRESHOLD_MASK,  DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHI=
FT,0x01aa,     GPU_CONFIGREG_DIDT_IND },
> +       {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_=
HI_POWER_THRESHOLD_MASK,  DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHI=
FT, 0x01aa,     GPU_CONFIGREG_DIDT_IND },
>         {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__UNUSE=
D_0_MASK,                 DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT,            =
   0x0000,     GPU_CONFIGREG_DIDT_IND },
>
>         {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__DIDT=
_TUNING_ENABLE_MASK,      DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, =
   0x0001,     GPU_CONFIGREG_DIDT_IND },
> @@ -666,8 +665,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Pola=
ris11_Kicker[] =3D
>         {   0xFFFFFFFF  }  /* End of list */
>  };
>
> -static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =3D
> -{
> +static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =3D {
>  // ---------------------------------------------------------------------=
---------------------------------------------------------------------------=
---------------------------------
>  //      Offset                             Mask                         =
                       Shift                                               =
Value       Type
>  // ---------------------------------------------------------------------=
---------------------------------------------------------------------------=
---------------------------------
> @@ -703,8 +701,7 @@ static const struct gpu_pt_config_reg GCCACConfig_Veg=
aM[] =3D
>      {   0xFFFFFFFF  }  // End of list
>  };
>
> -static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =3D
> -{
> +static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =3D {
>  // ---------------------------------------------------------------------=
---------------------------------------------------------------------------=
---------------------------------
>  //      Offset                             Mask                         =
                       Shift                                               =
Value       Type
>  // ---------------------------------------------------------------------=
---------------------------------------------------------------------------=
---------------------------------
> @@ -831,7 +828,7 @@ static const struct gpu_pt_config_reg DIDTConfig_Vega=
M[] =3D
>      {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_STA=
LL_CTRL_ENABLE_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, =
0x0001,     GPU_CONFIGREG_DIDT_IND },
>      {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_STA=
LL_DELAY_HI_MASK,      DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,    =
0x0001,     GPU_CONFIGREG_DIDT_IND },
>      {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_STA=
LL_DELAY_LO_MASK,      DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,    =
0x0001,     GPU_CONFIGREG_DIDT_IND },
> -    {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_HI_=
POWER_THRESHOLD_MASK,  DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,=
0x01aa,     GPU_CONFIGREG_DIDT_IND },
> +    {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__DIDT_HI_=
POWER_THRESHOLD_MASK,  DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT,=
 0x01aa,     GPU_CONFIGREG_DIDT_IND },
>      {   ixDIDT_TCP_STALL_CTRL,             DIDT_TCP_STALL_CTRL__UNUSED_0=
_MASK,                 DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT,               =
0x0000,     GPU_CONFIGREG_DIDT_IND },
>
>      {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__DIDT_TU=
NING_ENABLE_MASK,      DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT,    =
0x0001,     GPU_CONFIGREG_DIDT_IND },
> --
> 2.17.1
>