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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 7 Aug 2023 13:29:53 -0400
Message-ID: <CADnq5_MwqU2dumXc4tjkap63sv4ynni29M3=MTFngzmbZ0BbLw@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu: Clean up errors in nv.c
To:     Ran Sun <sunran001@208suo.com>
Cc:     alexander.deucher@amd.com, dri-devel@lists.freedesktop.org,
        amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org
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Applied.  Thanks!

On Wed, Aug 2, 2023 at 3:34=E2=80=AFAM Ran Sun <sunran001@208suo.com> wrote=
:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/nv.c | 48 +++++++++++----------------------
>  1 file changed, 16 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu=
/nv.c
> index 51523b27a186..414c3c85172d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -67,21 +67,18 @@
>  static const struct amd_ip_funcs nv_common_ip_funcs;
>
>  /* Navi */
> -static const struct amdgpu_video_codec_info nv_video_codecs_encode_array=
[] =3D
> -{
> +static const struct amdgpu_video_codec_info nv_video_codecs_encode_array=
[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 2304, 0)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 23=
04, 0)},
>  };
>
> -static const struct amdgpu_video_codecs nv_video_codecs_encode =3D
> -{
> +static const struct amdgpu_video_codecs nv_video_codecs_encode =3D {
>         .codec_count =3D ARRAY_SIZE(nv_video_codecs_encode_array),
>         .codec_array =3D nv_video_codecs_encode_array,
>  };
>
>  /* Navi1x */
> -static const struct amdgpu_video_codec_info nv_video_codecs_decode_array=
[] =3D
> -{
> +static const struct amdgpu_video_codec_info nv_video_codecs_decode_array=
[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4=
096, 3)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4=
096, 5)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
> @@ -91,8 +88,7 @@ static const struct amdgpu_video_codec_info nv_video_co=
decs_decode_array[] =3D
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 435=
2, 0)},
>  };
>
> -static const struct amdgpu_video_codecs nv_video_codecs_decode =3D
> -{
> +static const struct amdgpu_video_codecs nv_video_codecs_decode =3D {
>         .codec_count =3D ARRAY_SIZE(nv_video_codecs_decode_array),
>         .codec_array =3D nv_video_codecs_decode_array,
>  };
> @@ -108,8 +104,7 @@ static const struct amdgpu_video_codecs sc_video_code=
cs_encode =3D {
>         .codec_array =3D sc_video_codecs_encode_array,
>  };
>
> -static const struct amdgpu_video_codec_info sc_video_codecs_decode_array=
_vcn0[] =3D
> -{
> +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array=
_vcn0[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4=
096, 3)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4=
096, 5)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
> @@ -120,8 +115,7 @@ static const struct amdgpu_video_codec_info sc_video_=
codecs_decode_array_vcn0[]
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 435=
2, 0)},
>  };
>
> -static const struct amdgpu_video_codec_info sc_video_codecs_decode_array=
_vcn1[] =3D
> -{
> +static const struct amdgpu_video_codec_info sc_video_codecs_decode_array=
_vcn1[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4=
096, 3)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4=
096, 5)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
> @@ -131,27 +125,23 @@ static const struct amdgpu_video_codec_info sc_vide=
o_codecs_decode_array_vcn1[]
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 435=
2, 0)},
>  };
>
> -static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =3D
> -{
> +static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =3D =
{
>         .codec_count =3D ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
>         .codec_array =3D sc_video_codecs_decode_array_vcn0,
>  };
>
> -static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =3D
> -{
> +static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =3D =
{
>         .codec_count =3D ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
>         .codec_array =3D sc_video_codecs_decode_array_vcn1,
>  };
>
>  /* SRIOV Sienna Cichlid, not const since data is controlled by host */
> -static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array=
[] =3D
> -{
> +static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array=
[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 2160, 0)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 7680, 43=
52, 0)},
>  };
>
> -static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array=
_vcn0[] =3D
> -{
> +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array=
_vcn0[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4=
096, 3)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4=
096, 5)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
> @@ -162,8 +152,7 @@ static struct amdgpu_video_codec_info sriov_sc_video_=
codecs_decode_array_vcn0[]
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 435=
2, 0)},
>  };
>
> -static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array=
_vcn1[] =3D
> -{
> +static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array=
_vcn1[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4=
096, 3)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4=
096, 5)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
> @@ -173,20 +162,17 @@ static struct amdgpu_video_codec_info sriov_sc_vide=
o_codecs_decode_array_vcn1[]
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 435=
2, 0)},
>  };
>
> -static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =3D
> -{
> +static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =3D {
>         .codec_count =3D ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
>         .codec_array =3D sriov_sc_video_codecs_encode_array,
>  };
>
> -static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =3D
> -{
> +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =3D =
{
>         .codec_count =3D ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vc=
n0),
>         .codec_array =3D sriov_sc_video_codecs_decode_array_vcn0,
>  };
>
> -static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =3D
> -{
> +static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =3D =
{
>         .codec_count =3D ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vc=
n1),
>         .codec_array =3D sriov_sc_video_codecs_decode_array_vcn1,
>  };
> @@ -536,8 +522,7 @@ static void nv_program_aspm(struct amdgpu_device *ade=
v)
>
>  }
>
> -const struct amdgpu_ip_block_version nv_common_ip_block =3D
> -{
> +const struct amdgpu_ip_block_version nv_common_ip_block =3D {
>         .type =3D AMD_IP_BLOCK_TYPE_COMMON,
>         .major =3D 1,
>         .minor =3D 0,
> @@ -642,8 +627,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_=
device *adev,
>         return 0;
>  }
>
> -static const struct amdgpu_asic_funcs nv_asic_funcs =3D
> -{
> +static const struct amdgpu_asic_funcs nv_asic_funcs =3D {
>         .read_disabled_bios =3D &nv_read_disabled_bios,
>         .read_bios_from_rom =3D &amdgpu_soc15_read_bios_from_rom,
>         .read_register =3D &nv_read_register,
> --
> 2.17.1
>