Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20230802072127.12896-1-sunran001@208suo.com>
In-Reply-To: <20230802072127.12896-1-sunran001@208suo.com>
From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 7 Aug 2023 13:26:06 -0400
Message-ID: <CADnq5_NK9xz9OAoLkjKMtaZ+k+7PsOT7oeCacqap8MRs_9oG1g@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu: Clean up errors in soc21.c
To:     Ran Sun <sunran001@208suo.com>
Cc:     alexander.deucher@amd.com, dri-devel@lists.freedesktop.org,
        amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

Applied.  Thanks!

On Wed, Aug 2, 2023 at 3:21=E2=80=AFAM Ran Sun <sunran001@208suo.com> wrote=
:
>
> Fix the following errors reported by checkpatch:
>
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/soc21.c | 30 ++++++++++--------------------
>  1 file changed, 10 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amd=
gpu/soc21.c
> index e5e5d68a4d70..4f3ecd66eb6b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -48,33 +48,28 @@
>  static const struct amd_ip_funcs soc21_common_ip_funcs;
>
>  /* SOC21 */
> -static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encod=
e_array_vcn0[] =3D
> -{
> +static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encod=
e_array_vcn0[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 2304, 0)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 23=
04, 0)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 435=
2, 0)},
>  };
>
> -static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encod=
e_array_vcn1[] =3D
> -{
> +static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encod=
e_array_vcn1[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 2304, 0)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 23=
04, 0)},
>  };
>
> -static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vc=
n0 =3D
> -{
> +static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vc=
n0 =3D {
>         .codec_count =3D ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_v=
cn0),
>         .codec_array =3D vcn_4_0_0_video_codecs_encode_array_vcn0,
>  };
>
> -static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vc=
n1 =3D
> -{
> +static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vc=
n1 =3D {
>         .codec_count =3D ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_v=
cn1),
>         .codec_array =3D vcn_4_0_0_video_codecs_encode_array_vcn1,
>  };
>
> -static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decod=
e_array_vcn0[] =3D
> -{
> +static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decod=
e_array_vcn0[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 43=
52, 186)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 40=
96, 0)},
> @@ -82,22 +77,19 @@ static const struct amdgpu_video_codec_info vcn_4_0_0=
_video_codecs_decode_array_
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 435=
2, 0)},
>  };
>
> -static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decod=
e_array_vcn1[] =3D
> -{
> +static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decod=
e_array_vcn1[] =3D {
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 409=
6, 4096, 52)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 43=
52, 186)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 40=
96, 0)},
>         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 435=
2, 0)},
>  };
>
> -static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vc=
n0 =3D
> -{
> +static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vc=
n0 =3D {
>         .codec_count =3D ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_v=
cn0),
>         .codec_array =3D vcn_4_0_0_video_codecs_decode_array_vcn0,
>  };
>
> -static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vc=
n1 =3D
> -{
> +static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vc=
n1 =3D {
>         .codec_count =3D ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_v=
cn1),
>         .codec_array =3D vcn_4_0_0_video_codecs_decode_array_vcn1,
>  };
> @@ -445,8 +437,7 @@ static void soc21_program_aspm(struct amdgpu_device *=
adev)
>                 adev->nbio.funcs->program_aspm(adev);
>  }
>
> -const struct amdgpu_ip_block_version soc21_common_ip_block =3D
> -{
> +const struct amdgpu_ip_block_version soc21_common_ip_block =3D {
>         .type =3D AMD_IP_BLOCK_TYPE_COMMON,
>         .major =3D 1,
>         .minor =3D 0,
> @@ -547,8 +538,7 @@ static int soc21_update_umd_stable_pstate(struct amdg=
pu_device *adev,
>         return 0;
>  }
>
> -static const struct amdgpu_asic_funcs soc21_asic_funcs =3D
> -{
> +static const struct amdgpu_asic_funcs soc21_asic_funcs =3D {
>         .read_disabled_bios =3D &soc21_read_disabled_bios,
>         .read_bios_from_rom =3D &amdgpu_soc15_read_bios_from_rom,
>         .read_register =3D &soc21_read_register,
> --
> 2.17.1
>