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Message-ID: <15c2fed5-d2b7-3b25-8aa6-95453afee716@quicinc.com>
Date:   Tue, 8 Aug 2023 14:59:01 +0800
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Subject: Re: [PATCH 2/3] dt-bindings: clock: add qca8386/qca8084 clock and
 reset definitions
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        <agross@kernel.org>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <mturquette@baylibre.com>,
        <sboyd@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <p.zabel@pengutronix.de>
CC:     <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_srichara@quicinc.com>
References: <20230801085352.22873-1-quic_luoj@quicinc.com>
 <20230801085352.22873-3-quic_luoj@quicinc.com>
 <ef996a7e-6eba-4366-c3ea-0d08f2768e98@linaro.org>
 <cf9788f0-a115-5ff9-1195-f4f302551e04@quicinc.com>
 <d1172ed6-ee3b-83b6-1656-c91e35fbc2df@linaro.org>
 <f25e1043-6dfa-2dcc-2948-88025f4881d8@quicinc.com>
 <1f20d778-cdae-d6d9-ac86-744dd45176d3@linaro.org>
From:   Jie Luo <quic_luoj@quicinc.com>
In-Reply-To: <1f20d778-cdae-d6d9-ac86-744dd45176d3@linaro.org>
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On 8/8/2023 2:46 PM, Krzysztof Kozlowski wrote:
> On 08/08/2023 08:31, Jie Luo wrote:
>>
>>
>> On 8/8/2023 1:57 PM, Krzysztof Kozlowski wrote:
>>> On 08/08/2023 07:19, Jie Luo wrote:
>>>>>> +properties:
>>>>>> +  compatible:
>>>>>> +    const: qcom,nsscc-qca8k
>>>>>
>>>>> SoC name is before IP block names. See:
>>>>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>>>>
>>>>> qca8k is not SoC specific. I don't know what you are documenting here,
>>>>> but if this is a SoC, then follow SoC rules.
>>>>>
>>>>> If this is not SoC, it confuses me a bit to use GCC binding.
>>>>>
>>>>> Anyway, this was not tested, as pointed out by bot... Please test the
>>>>> code before sending.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Hi Krzysztof,
>>>>
>>>> Thanks for the review comments.
>>>> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
>>>> the hardware register is accessed by MDIO bus, which is not a SOC.
>>>>
>>>> But it has the self-contained clock controller system, the clock
>>>> framework of qca8386/qca8084 is same as the GCC of ipq platform such as
>>>> ipq9574.
>>>
>>> OK
>>>
>>>>
>>>> would you help advise whether we can document it with the compatible
>>>> "qcom,qca8k-nsscc"?
>>>
>>> For example:
>>> qcom,qca8084-nsscc
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Thanks Krzysztof for the suggestion.
>>
>> i will document the compatible below.
>> "qcom,qca8084-nsscc" for the PHY mode of device.
>> "qcom,qca8386-nsscc" for the switch mode of device.
> 
> The clocks seem to be exactly the same for both, so use only one
> compatible in the driver (the fallback) and oneOf in the bindings like:
> 
> https://elixir.bootlin.com/linux/v6.3-rc6/source/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml#L31
> 
> Best regards,
> Krzysztof
> 
Yes, it is the same driver for both.
i will update this in the next patch set, thanks Krzysztof.

Jie.