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Message-ID: <d1172ed6-ee3b-83b6-1656-c91e35fbc2df@linaro.org>
Date:   Tue, 8 Aug 2023 07:57:19 +0200
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Subject: Re: [PATCH 2/3] dt-bindings: clock: add qca8386/qca8084 clock and
 reset definitions
To:     Jie Luo <quic_luoj@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, konrad.dybcio@linaro.org,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        p.zabel@pengutronix.de
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        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        quic_srichara@quicinc.com
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 <cf9788f0-a115-5ff9-1195-f4f302551e04@quicinc.com>
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From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <cf9788f0-a115-5ff9-1195-f4f302551e04@quicinc.com>
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On 08/08/2023 07:19, Jie Luo wrote:
>>> +properties:
>>> +  compatible:
>>> +    const: qcom,nsscc-qca8k
>>
>> SoC name is before IP block names. See:
>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>
>> qca8k is not SoC specific. I don't know what you are documenting here,
>> but if this is a SoC, then follow SoC rules.
>>
>> If this is not SoC, it confuses me a bit to use GCC binding.
>>
>> Anyway, this was not tested, as pointed out by bot... Please test the
>> code before sending.
>>
>> Best regards,
>> Krzysztof
>>
> 
> Hi Krzysztof,
> 
> Thanks for the review comments.
> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
> the hardware register is accessed by MDIO bus, which is not a SOC.
> 
> But it has the self-contained clock controller system, the clock 
> framework of qca8386/qca8084 is same as the GCC of ipq platform such as 
> ipq9574.

OK

> 
> would you help advise whether we can document it with the compatible
> "qcom,qca8k-nsscc"?

For example:
qcom,qca8084-nsscc

Best regards,
Krzysztof