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Date:   Wed, 9 Aug 2023 14:53:33 +1000
From:   Stephen Rothwell <sfr@canb.auug.org.au>
To:     Yury Norov <yury.norov@gmail.com>,
        David Miller <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>
Cc:     Networking <netdev@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Linux Next Mailing List <linux-next@vger.kernel.org>,
        Maher Sanalla <msanalla@nvidia.com>,
        Saeed Mahameed <saeedm@nvidia.com>
Subject: linux-next: manual merge of the bitmap tree with the net-next tree
Message-ID: <20230809145333.03f31309@canb.auug.org.au>
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Hi all,

Today's linux-next merge of the bitmap tree got a conflict in:

  drivers/net/ethernet/mellanox/mlx5/core/eq.c

between commits:

  54b2cf41b853 ("net/mlx5: Refactor completion IRQ request/release handlers=
 in EQ layer")
  ddd2c79da020 ("net/mlx5: Introduce mlx5_cpumask_default_spread")

from the net-next tree and commit:

  a4be5fa84bb2 ("net: mlx5: switch comp_irqs_request() to using for_each_nu=
ma_cpu")

from the bitmap tree.

I fixed it up (I think - see below) and can carry the fix as
necessary. This is now fixed as far as linux-next is concerned, but any
non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging.  You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.

--=20
Cheers,
Stephen Rothwell

diff --cc drivers/net/ethernet/mellanox/mlx5/core/eq.c
index ea0405e0a43f,7c8dc0443d6a..000000000000
--- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c
@@@ -815,112 -803,82 +815,105 @@@ void mlx5_eq_update_ci(struct mlx5_eq *
  }
  EXPORT_SYMBOL(mlx5_eq_update_ci);
 =20
 -static void comp_irqs_release_pci(struct mlx5_core_dev *dev)
 +static void comp_irq_release_pci(struct mlx5_core_dev *dev, u16 vecidx)
  {
  	struct mlx5_eq_table *table =3D dev->priv.eq_table;
 +	struct mlx5_irq *irq;
 =20
 -	mlx5_irqs_release_vectors(table->comp_irqs, table->num_comp_eqs);
 +	irq =3D xa_load(&table->comp_irqs, vecidx);
 +	if (!irq)
 +		return;
 +
 +	xa_erase(&table->comp_irqs, vecidx);
 +	mlx5_irq_release_vector(irq);
  }
 =20
 -static int comp_irqs_request_pci(struct mlx5_core_dev *dev)
 +static int mlx5_cpumask_default_spread(int numa_node, int index)
  {
- 	const struct cpumask *prev =3D cpu_none_mask;
- 	const struct cpumask *mask;
 -	struct mlx5_eq_table *table =3D dev->priv.eq_table;
 -	int ncomp_eqs;
 -	u16 *cpus;
 -	int ret;
 +	int found_cpu =3D 0;
 +	int i =3D 0;
- 	int cpu;
+ 	int cpu, hop;
 -	int i;
 =20
 -	ncomp_eqs =3D table->num_comp_eqs;
 -	cpus =3D kcalloc(ncomp_eqs, sizeof(*cpus), GFP_KERNEL);
 -	if (!cpus)
 -		return -ENOMEM;
 -
 -	i =3D 0;
  	rcu_read_lock();
- 	for_each_numa_hop_mask(mask, numa_node) {
- 		for_each_cpu_andnot(cpu, mask, prev) {
- 			if (i++ =3D=3D index) {
- 				found_cpu =3D cpu;
- 				goto spread_done;
- 			}
 -	for_each_numa_online_cpu(cpu, hop, dev->priv.numa_node) {
 -		cpus[i] =3D cpu;
 -		if (++i =3D=3D ncomp_eqs)
++	for_each_numa_online_cpu(cpu, hop, numa_node) {
++		if (i++ =3D=3D index) {
++			found_cpu =3D cpu;
+ 			break;
 +		}
- 		prev =3D mask;
  	}
-=20
- spread_done:
  	rcu_read_unlock();
 -	ret =3D mlx5_irqs_request_vectors(dev, cpus, ncomp_eqs, table->comp_irqs=
, &table->rmap);
 -	kfree(cpus);
 -	return ret;
 +	return found_cpu;
  }
 =20
 -static void comp_irqs_release_sf(struct mlx5_core_dev *dev)
 +static struct cpu_rmap *mlx5_eq_table_get_pci_rmap(struct mlx5_core_dev *=
dev)
  {
 -	struct mlx5_eq_table *table =3D dev->priv.eq_table;
 -
 -	mlx5_irq_affinity_irqs_release(dev, table->comp_irqs, table->num_comp_eq=
s);
 +#ifdef CONFIG_RFS_ACCEL
 +#ifdef CONFIG_MLX5_SF
 +	if (mlx5_core_is_sf(dev))
 +		return dev->priv.parent_mdev->priv.eq_table->rmap;
 +#endif
 +	return dev->priv.eq_table->rmap;
 +#else
 +	return NULL;
 +#endif
  }
 =20
 -static int comp_irqs_request_sf(struct mlx5_core_dev *dev)
 +static int comp_irq_request_pci(struct mlx5_core_dev *dev, u16 vecidx)
  {
  	struct mlx5_eq_table *table =3D dev->priv.eq_table;
 -	int ncomp_eqs =3D table->num_comp_eqs;
 +	struct cpu_rmap *rmap;
 +	struct mlx5_irq *irq;
 +	int cpu;
 =20
 -	return mlx5_irq_affinity_irqs_request_auto(dev, ncomp_eqs, table->comp_i=
rqs);
 +	rmap =3D mlx5_eq_table_get_pci_rmap(dev);
 +	cpu =3D mlx5_cpumask_default_spread(dev->priv.numa_node, vecidx);
 +	irq =3D mlx5_irq_request_vector(dev, cpu, vecidx, &rmap);
 +	if (IS_ERR(irq))
 +		return PTR_ERR(irq);
 +
 +	return xa_err(xa_store(&table->comp_irqs, vecidx, irq, GFP_KERNEL));
  }
 =20
 -static void comp_irqs_release(struct mlx5_core_dev *dev)
 +static void comp_irq_release_sf(struct mlx5_core_dev *dev, u16 vecidx)
  {
  	struct mlx5_eq_table *table =3D dev->priv.eq_table;
 +	struct mlx5_irq *irq;
 =20
 -	mlx5_core_is_sf(dev) ? comp_irqs_release_sf(dev) :
 -			       comp_irqs_release_pci(dev);
 +	irq =3D xa_load(&table->comp_irqs, vecidx);
 +	if (!irq)
 +		return;
 =20
 -	kfree(table->comp_irqs);
 +	xa_erase(&table->comp_irqs, vecidx);
 +	mlx5_irq_affinity_irq_release(dev, irq);
  }
 =20
 -static int comp_irqs_request(struct mlx5_core_dev *dev)
 +static int comp_irq_request_sf(struct mlx5_core_dev *dev, u16 vecidx)
  {
  	struct mlx5_eq_table *table =3D dev->priv.eq_table;
 -	int ncomp_eqs;
 -	int ret;
 +	struct mlx5_irq *irq;
 =20
 -	ncomp_eqs =3D table->num_comp_eqs;
 -	table->comp_irqs =3D kcalloc(ncomp_eqs, sizeof(*table->comp_irqs), GFP_K=
ERNEL);
 -	if (!table->comp_irqs)
 -		return -ENOMEM;
 +	irq =3D mlx5_irq_affinity_irq_request_auto(dev, &table->used_cpus, vecid=
x);
 +	if (IS_ERR(irq)) {
 +		/* In case SF irq pool does not exist, fallback to the PF irqs*/
 +		if (PTR_ERR(irq) =3D=3D -ENOENT)
 +			return comp_irq_request_pci(dev, vecidx);
 =20
 -	ret =3D mlx5_core_is_sf(dev) ? comp_irqs_request_sf(dev) :
 -				     comp_irqs_request_pci(dev);
 -	if (ret < 0)
 -		kfree(table->comp_irqs);
 +		return PTR_ERR(irq);
 +	}
 =20
 -	return ret;
 +	return xa_err(xa_store(&table->comp_irqs, vecidx, irq, GFP_KERNEL));
 +}
 +
 +static void comp_irq_release(struct mlx5_core_dev *dev, u16 vecidx)
 +{
 +	mlx5_core_is_sf(dev) ? comp_irq_release_sf(dev, vecidx) :
 +			       comp_irq_release_pci(dev, vecidx);
 +}
 +
 +static int comp_irq_request(struct mlx5_core_dev *dev, u16 vecidx)
 +{
 +	return mlx5_core_is_sf(dev) ? comp_irq_request_sf(dev, vecidx) :
 +				      comp_irq_request_pci(dev, vecidx);
  }
 =20
  #ifdef CONFIG_RFS_ACCEL

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