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Received: from DM8PR01MB6824.prod.exchangelabs.com (2603:10b6:8:23::24) by PH0PR01MB6229.prod.exchangelabs.com (2603:10b6:510:1f::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.28; Wed, 9 Aug 2023 09:17:37 +0000 Received: from DM8PR01MB6824.prod.exchangelabs.com ([fe80::d62f:d774:15b0:4a40]) by DM8PR01MB6824.prod.exchangelabs.com ([fe80::d62f:d774:15b0:4a40%4]) with mapi id 15.20.6652.026; Wed, 9 Aug 2023 09:17:36 +0000 Message-ID: <1bb556dc-8adc-63ea-75b3-ad0596f1b89e@amperemail.onmicrosoft.com> Date: Wed, 9 Aug 2023 17:17:26 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH] perf/core: fix the bug in the event multiplexing To: Oliver Upton , Huang Shijie Cc: maz@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, pbonzini@redhat.com, peterz@infradead.org, ingo@redhat.com, acme@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, patches@amperecomputing.com, zwang@amperecomputing.com References: <20230809013953.7692-1-shijie@os.amperecomputing.com> From: Shijie Huang In-Reply-To: Content-Type: text/plain; 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Root cause. >> There is only 7 counters in my arm64 platform: >> (one cycle counter) + (6 normal counters) >> >> In 1.3 above, we will use 10 event counters. >> Since we only have 7 counters, the perf core will trigger >> event multiplexing in hrtimer: >> merge_sched_in() -->perf_mux_hrtimer_restart() --> >> perf_rotate_context(). >> >> In the perf_rotate_context(), it does not restore some PMU registers >> as context_switch() does. In context_switch(): >> kvm_sched_in() --> kvm_vcpu_pmu_restore_guest() >> kvm_sched_out() --> kvm_vcpu_pmu_restore_host() >> >> So we got wrong result. > This is a rather vague description of the problem. AFAICT, the > issue here is on VHE systems we wind up getting the EL0 count > enable/disable bits backwards when entering the guest, which is > corroborated by the data you have below. > >> +void arch_perf_rotate_pmu_set(void) >> +{ >> + if (is_guest()) >> + kvm_vcpu_pmu_restore_guest(NULL); >> + else >> + kvm_vcpu_pmu_restore_host(NULL); >> +} >> + > This sort of hook is rather nasty, and I'd strongly prefer a solution > that's confined to KVM. I don't think the !is_guest() branch is > necessary at all. Regardless of how the pmu context is changed, we need > to go through vcpu_put() before getting back out to userspace. > > We can check for a running vCPU (ick) from kvm_set_pmu_events() and either > do the EL0 bit flip there or make a request on the vCPU to call > kvm_vcpu_pmu_restore_guest() immediately before reentering the guest. > I'm slightly leaning towards the latter, unless anyone has a better idea > here. Thanks a lot, I will check the code about the latter one, and try to fix it again. Thanks Huang Shijie