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Date:   Wed, 9 Aug 2023 17:00:51 +0800
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Subject: Re: [PATCH v5 15/19] KVM:x86: Optimize CET supervisor SSP save/reload
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To:     Chao Gao <chao.gao@intel.com>
CC:     <seanjc@google.com>, <pbonzini@redhat.com>, <peterz@infradead.org>,
        <john.allen@amd.com>, <kvm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <rick.p.edgecombe@intel.com>,
        <binbin.wu@linux.intel.com>
References: <20230803042732.88515-1-weijiang.yang@intel.com>
 <20230803042732.88515-16-weijiang.yang@intel.com>
 <ZMy6INjzYiVqOKEy@chao-email>
From:   "Yang, Weijiang" <weijiang.yang@intel.com>
In-Reply-To: <ZMy6INjzYiVqOKEy@chao-email>
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On 8/4/2023 4:43 PM, Chao Gao wrote:
> On Thu, Aug 03, 2023 at 12:27:28AM -0400, Yang Weijiang wrote:
>> Make PL{0,1,2}_SSP as write-intercepted to detect whether
>> guest is using these MSRs. Disable intercept to the MSRs
>> if they're written with non-zero values. KVM does save/
>> reload for the MSRs only if they're used by guest.
> What would happen if guest tries to use XRSTORS to load S_CET state from a
> xsave area without any writes to the PL0-2_SSP (i.e., at that point, writes to
> the MSRs are still intercepted)?
I need to do some experiments to get the details, but now expect some kind
of error in guest is seen.
>> @@ -2420,6 +2432,14 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>> 		else
>> 			vmx->pt_desc.guest.addr_a[index / 2] = data;
>> 		break;
>> +	case MSR_IA32_PL0_SSP ... MSR_IA32_PL2_SSP:
>> +		if (kvm_set_msr_common(vcpu, msr_info))
>> +			return 1;
>> +		if (data) {
>> +			vmx_disable_write_intercept_sss_msr(vcpu);
>> +			wrmsrl(msr_index, data);
> Is it necessary to do the wrmsl()?
> looks the next kvm_x86_prepare_switch_to_guest() will load PL0-2_SSP from the
> caching values.
Oh, yes, it's not necessary after moving the reload logic to kvm_x86_prepare_switch_to_guest().
Thanks!