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From:   "Fabio M. De Francesco" <fmdefrancesco@gmail.com>
To:     Mike Rapoport <rppt@kernel.org>
Cc:     Jonathan Corbet <corbet@lwn.net>,
        Jonathan Cameron <Jonathan.Cameron@huawei.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mm@kvack.org, Andrew Morton <akpm@linux-foundation.org>,
        Ira Weiny <ira.weiny@intel.com>,
        Matthew Wilcox <willy@infradead.org>,
        Randy Dunlap <rdunlap@infradead.org>
Subject: Re: [PATCH] Documentation/page_tables: Add info about MMU/TLB and Page Faults
Date:   Wed, 09 Aug 2023 15:00:31 +0200
Message-ID: <3770829.kQq0lBPeGt@suse>
In-Reply-To: <20230807105010.GK2607694@kernel.org>
References: <20230728120054.12306-1-fmdefrancesco@gmail.com>
 <20230807105010.GK2607694@kernel.org>
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On luned=EC 7 agosto 2023 12:50:10 CEST Mike Rapoport wrote:
> Hi Fabio,
>=20
> On Fri, Jul 28, 2023 at 01:53:01PM +0200, Fabio M. De Francesco wrote:
> > Extend page_tables.rst by adding a section about the role of MMU and TLB
> > in translating between virtual addresses and physical page frames.
> > Furthermore explain the concept behind Page Faults and how the Linux
> > kernel handles TLB misses. Finally briefly explain how and why to disab=
le
> > the page faults handler.
> >=20
> > [snip]
> >
> > +MMU, TLB, and Page Faults
> > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D
> > +
> > +The `Memory Management Unit (MMU)` is a hardware component that handles
> > virtual +to physical address translations. It may use relatively small
> > caches in hardware +called `Translation Lookaside Buffers (TLBs)` and=20
`Page
> > Walk Caches` to speed up +these translations.
> > +
> > +When a process wants to access a memory location, the CPU provides a
> > virtual
> > +address to the MMU, which then uses the MMU to check access permission=
s=20
and
> > +dirty bits, and if possible it resolves the physical address and conse=
nts
> > the +requested type of access to the corresponding physical address.
>=20
> Essentially any access to a memory location involves the translation from
> virtual to physical, not only when processes access memory.

Mike,

I'm cutting everything from here on because I agree with your comments, so =
I=20
could just write a long list of 'I agree', 'I understand' and the like. I w=
ant=20
to avoid readers from the aforementioned list :-)

I think (actually, I hope) that I have understood everything correctly. I w=
ill=20
send a new version with the necessary corrections by the end of this week.

Thanks again for your comments and suggestions.

=46abio