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Subject: Re: [PATCH v2 0/2] iommu/arm-smmu-v3: Add support for ECMDQ register
 mode
To:     Will Deacon <will@kernel.org>
Cc:     Robin Murphy <robin.murphy@arm.com>,
        Joerg Roedel <joro@8bytes.org>, iommu@lists.linux.dev,
        linux-kernel@vger.kernel.org,
        Zhen Lei <thunder.leizhen@huawei.com>,
        Tanmay Jagdale <tanmay@marvell.com>,
        Jonathan Cameron <Jonathan.Cameron@Huawei.com>, jgg@ziepe.ca
References: <20230809131303.1355-1-thunder.leizhen@huaweicloud.com>
 <20230809135603.GE4226@willie-the-truck>
From:   "Leizhen (ThunderTown)" <thunder.leizhen@huaweicloud.com>
Message-ID: <eaa7758e-9ff4-a039-7f94-734f63c72ba6@huaweicloud.com>
Date:   Thu, 10 Aug 2023 10:18:36 +0800
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On 2023/8/9 21:56, Will Deacon wrote:
> On Wed, Aug 09, 2023 at 09:13:01PM +0800, thunder.leizhen@huaweicloud.com wrote:
>> From: Zhen Lei <thunder.leizhen@huawei.com>
>>
>> v1 --> v2:
> 
> Jason previously asked about performance numbers for ECMDQ:
> 
> https://lore.kernel.org/r/ZL6n3f01yV7tc4yH@ziepe.ca
> 
> Do you have any?

I asked my colleagues in the chip department, and they said that the chip
was not commercially available and the specific data could not be disclosed.
However, to be sure, the performance has improved, but not by much, the
public benchmark is only about 5%. Your optimization patch was so perfect
that it ruined our jobs.

However, since Marvell also implements ECMDQ, there are at least two users.
Do we think about making it available first?

> 
> Will
> .
> 

-- 
Regards,
  Zhen Lei