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Subject: Re: [RFC PATCH v5 5/5] riscv/cmpxchg: Implement xchg for variables
 of size 1 and 2
From:   Leonardo =?ISO-8859-1?Q?Br=E1s?= <leobras@redhat.com>
To:     Arnd Bergmann <arnd@arndb.de>, Will Deacon <will@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Boqun Feng <boqun.feng@gmail.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Andrea Parri <parri.andrea@gmail.com>,
        Andrzej Hajda <andrzej.hajda@intel.com>,
        Palmer Dabbelt <palmer@rivosinc.com>,
        guoren <guoren@kernel.org>
Cc:     linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Date:   Thu, 10 Aug 2023 13:04:04 -0300
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         <20230810040349.92279-7-leobras@redhat.com>
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On Thu, 2023-08-10 at 08:51 +0200, Arnd Bergmann wrote:
> On Thu, Aug 10, 2023, at 06:03, Leonardo Bras wrote:
> > xchg for variables of size 1-byte and 2-bytes is not yet available for
> > riscv, even though its present in other architectures such as arm64 and
> > x86. This could lead to not being able to implement some locking mechan=
isms
> > or requiring some rework to make it work properly.
> >=20
> > Implement 1-byte and 2-bytes xchg in order to achieve parity with other
> > architectures.
> >=20
> > Signed-off-by: Leonardo Bras <leobras@redhat.com>
>=20

Hello Arnd Bergmann, thanks for reviewing!

> Parity with other architectures by itself is not a reason to do this,
> in particular the other architectures you listed have the instructions
> in hardware while riscv does not.

Sure, I understand RISC-V don't have native support for xchg on variables o=
f
size < 4B. My argument is that it's nice to have even an emulated version f=
or
this in case any future mechanism wants to use it.

Not having it may mean we won't be able to enable given mechanism in RISC-V=
.=20

>=20
> Emulating the small xchg() through cmpxchg() is particularly tricky
> since it's easy to run into a case where this does not guarantee
> forward progress.
>=20

Didn't get this part:
By "emulating small xchg() through cmpxchg()", did you mean like emulating =
an
xchg (usually 1 instruction) with lr & sc (same used in cmpxchg) ?

If so, yeah, it's a fair point: in some extreme case we could have multiple
threads accessing given cacheline and have sc always failing. On the other =
hand,
there are 2 arguments on that:

1 - Other architectures, (such as powerpc, arm and arm64 without LSE atomic=
s)
also seem to rely in this mechanism for every xchg size. Another archs like=
 csky
and loongarch use asm that look like mine to handle size < 4B xchg.=20
   =20

>  This is also something that almost no architecture
> specific code relies on (generic qspinlock being a notable exception).
>=20

2 - As you mentioned, there should be very little code that will actually m=
ake
use of xchg for vars < 4B, so it should be safe to assume its fine to not
guarantee forward progress for those rare usages (like some of above mentio=
ned
archs).

> I would recommend just dropping this patch from the series, at least
> until there is a need for it.

While I agree this is a valid point, I believe its more interesting to have=
 it
implemented if any future mechanism wants to make use of this.=20


Thanks!
Leo