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Thu, 10 Aug 2023 20:16:14 -0700 (PDT) Received: from [10.72.112.92] ([43.228.180.230]) by smtp.gmail.com with ESMTPSA id s88-20020a17090a69e100b00265c742a262sm2400175pjj.4.2023.08.10.20.16.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Aug 2023 20:16:13 -0700 (PDT) Message-ID: <60a2cc0e-df09-4305-6bfc-25b3d864040a@redhat.com> Date: Fri, 11 Aug 2023 11:16:06 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v8 08/14] arm64: tlb: Implement __flush_s2_tlb_range_op() Content-Language: en-US To: Raghavendra Rao Ananta , Oliver Upton , Marc Zyngier , James Morse , Suzuki K Poulose Cc: Paolo Bonzini , Sean Christopherson , Huacai Chen , Zenghui Yu , Anup Patel , Atish Patra , Jing Zhang , Reiji Watanabe , Colton Lewis , David Matlack , Fuad Tabba , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-mips@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org References: <20230808231330.3855936-1-rananta@google.com> <20230808231330.3855936-9-rananta@google.com> From: Shaoqin Huang In-Reply-To: <20230808231330.3855936-9-rananta@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/9/23 07:13, Raghavendra Rao Ananta wrote: > Define __flush_s2_tlb_range_op(), as a wrapper over > __flush_tlb_range_op(), for stage-2 specific range-based TLBI > operations that doesn't necessarily have to deal with 'asid' > and 'tlbi_user' arguments. > > Signed-off-by: Raghavendra Rao Ananta Reviewed-by: Shaoqin Huang > --- > arch/arm64/include/asm/tlbflush.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index b9475a852d5be..93f4b397f9a12 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -340,6 +340,9 @@ do { \ > } \ > } while (0) > > +#define __flush_s2_tlb_range_op(op, start, pages, stride, tlb_level) \ > + __flush_tlb_range_op(op, start, pages, stride, 0, tlb_level, false) > + > static inline void __flush_tlb_range(struct vm_area_struct *vma, > unsigned long start, unsigned long end, > unsigned long stride, bool last_level, -- Shaoqin