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Date:   Fri, 11 Aug 2023 07:43:43 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Xingyu Wu <xingyu.wu@starfivetech.com>
CC:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>,
        Conor Dooley <conor@kernel.org>,
        Hal Feng <hal.feng@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v1] clk: starfive: jh7110-sys: Set PLL0 rate to 1.5GHz
Message-ID: <20230811-jiffy-nebula-a8ea5ef15eee@wendy>
References: <20230811033631.160912-1-xingyu.wu@starfivetech.com>
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On Fri, Aug 11, 2023 at 11:36:31AM +0800, Xingyu Wu wrote:
> Set PLL0 rate to 1.5GHz.

Why are you doing that though?


> Change the parent of cpu_root clock
> and the divider of cpu_core before setting.
>=20
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
>=20
> Hi Stephen and Emil,
>=20
> This patch sets PLL0 rate to 1.5GHz. In order not to affect the cpu=20
> operation, the cpu_root's parent clock should be changed first.
> And the divider of the cpu_core clock should be set to 2 so they
> won't crash when setting 1.5GHz without voltage regulation.
>=20
> This patch is based on linux-next which has merge PLL driver on
> StarFive JH7110 SoC.
>=20
> Thanks,
> Xingyu Wu

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