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Message-ID: <9a55016f-0049-f185-f2be-d138fe33384b@quicinc.com>
Date:   Fri, 11 Aug 2023 19:49:53 +0800
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Subject: Re: [PATCH v3 3/3] clk: qcom: add clock controller driver for
 qca8386/qca8084
To:     Konrad Dybcio <konrad.dybcio@linaro.org>, <andersson@kernel.org>,
        <agross@kernel.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <conor+dt@kernel.org>, <catalin.marinas@arm.com>,
        <will@kernel.org>, <p.zabel@pengutronix.de>
CC:     <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <quic_srichara@quicinc.com>
References: <20230810115419.25539-1-quic_luoj@quicinc.com>
 <20230810115419.25539-4-quic_luoj@quicinc.com>
 <9dec09fa-a5a3-416c-9b4d-4b4c4e10320b@linaro.org>
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From:   Jie Luo <quic_luoj@quicinc.com>
In-Reply-To: <9dec09fa-a5a3-416c-9b4d-4b4c4e10320b@linaro.org>
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On 8/10/2023 8:59 PM, Konrad Dybcio wrote:
> On 10.08.2023 13:54, Luo Jie wrote:
>> Add clock & reset controller driver for qca8386/qca8084.
>>
>> Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
>> ---
> 
>> +struct qcom_cc {
>> +	struct qcom_reset_controller reset;
>> +	struct clk_regmap **rclks;
>> +	size_t num_rclks;
>> +};
> This all, including the probe func, is required because of the MDIO dance,
> I assume?
> 
> Commonizing that would make more sense should more clocks like this appear
> in the future.
> 
Hi Konrad,
Thanks for the review.
the structure qcom_cc is not because of MDIO dance, this is the common 
structure used by other qcom clock drivers such as gcc-ipq9574 in the 
probe function.

seems that we can't make any more commonization on this, please let me 
know if there is any idea on this.

> [...]
> 
>> +static struct clk_branch nss_cc_switch_core_clk = {
>> +	.halt_reg = 0x8,
>> +	.clkr = {
>> +		.enable_reg = 0x8,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(const struct clk_init_data) {
>> +			.name = "nss_cc_switch_core_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +				&nss_cc_switch_core_clk_src.clkr.hw,
>> +			},
>> +			.num_parents = 1,
>> +			/* Can be disabled in PHY mode for power saving */
> Well it clearly cannot be disabled if it has the CLK_IS_CRITICAL flag :D
> 
> What's the "PHY mode" you're talking about?
Yes, the clock with flag CLK_IS_CRITICAL needs to be enabled, the 
hardware register needs to be configured to enable it, it is disabled by 
default.

this clock branch is necessary for the switch mode that has switch 
features such routing and fdb forwarding, i will remove the 
CLK_IS_CRITICAL from the clock that is not needed for the PHY mode, we 
can enable it later when configuring it as switch mode.

As for PHY mode, the device works as only PHY device, that includes 4 
PHY ports, no switch functions.

> 
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_mdio_ops,
>> +		},
>> +	},
>> +};
> I see a whole bunch of CRITICAL clocks.. please make sure these clocks
> are actually necessary for Linux to know about (i.e. if we don't need
> to call any operations on them, we might just skip registering them
> with the driver).
> 
> Konrad
> 
yes, Konrad, the clocks with  CLK_IS_CRITICAL need to be enabled 
manually, all clocks are disabled after reset(by default).