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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PUZP153MB0635.APCP153.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 7af4e8db-bdd9-417f-a652-08db9a55e94e X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Aug 2023 10:29:57.9842 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: VOKw9NKFG1OCSpT8DlDiGL+K/GfxVx6XvE7mrUq0dFPRTXxOx1i048k9yQZZthKEHe9SuZygCHooOAnnn9riog== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI2P153MB0444 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Michael Kelley (LINUX) > Sent: Thursday, August 3, 2023 12:19 AM > To: Saurabh Sengar ; tglx@linutronix.de; > mingo@redhat.com; bp@alien8.de; dave.hansen@linux.intel.com; > x86@kernel.org; hpa@zytor.com; luto@kernel.org; peterz@infradead.org; > linux-kernel@vger.kernel.org > Subject: [EXTERNAL] RE: [PATCH] x86/numa: Add Devicetree support >=20 > From: Saurabh Sengar Sent: Tuesday, June > 27, 2023 12:28 AM > > > > Hyper-V has usecases where it need to fetch NUMA information from > > Devicetree. Currently, it is not possible to extract the NUMA > > information from Devicetree for x86 arch. > > > > Add support for Devicetree in the x86_numa_init function, allowing the > > retrieval of NUMA node information from the Devicetree. > > > > Additionally, relocate the x86_dtb_init function before initmem_init > > to ensure the Devicetree initialization prior to its utilization in > > x86_numa_init. > > > > Signed-off-by: Saurabh Sengar > > --- > > arch/x86/Kconfig | 1 + > > arch/x86/kernel/setup.c | 2 +- > > arch/x86/mm/numa.c | 3 +++ > > 3 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index > > c531b16ee0bf..a2ada193b2d8 100644 > > --- a/arch/x86/Kconfig > > +++ b/arch/x86/Kconfig > > @@ -1567,6 +1567,7 @@ config NUMA > > depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP) > > default y if X86_BIGSMP > > select USE_PERCPU_NUMA_NODE_ID > > + select OF_NUMA if OF > > help > > Enable NUMA (Non-Uniform Memory Access) support. > > > > diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index > > fd975a4a5200..940c92a6a5e9 100644 > > --- a/arch/x86/kernel/setup.c > > +++ b/arch/x86/kernel/setup.c > > @@ -1220,6 +1220,7 @@ void __init setup_arch(char **cmdline_p) > > > > early_acpi_boot_init(); > > > > + x86_dtb_init(); > > initmem_init(); > > dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT); > > > > @@ -1261,7 +1262,6 @@ void __init setup_arch(char **cmdline_p) > > * Read APIC and some other early information from ACPI tables. > > */ > > acpi_boot_init(); > > - x86_dtb_init(); > > > > /* > > * get boot-time SMP configuration: > > diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index > > 2aadb2019b4f..a6d3d331fda2 100644 > > --- a/arch/x86/mm/numa.c > > +++ b/arch/x86/mm/numa.c > > @@ -11,6 +11,7 @@ > > #include > > #include > > #include > > +#include > > > > #include > > #include > > @@ -733,6 +734,8 @@ void __init x86_numa_init(void) > > if (!numa_init(amd_numa_init)) > > return; > > #endif > > + if (acpi_disabled && !numa_init(of_numa_init)) > > + return; > > } > > > > numa_init(dummy_numa_init); > > -- > > 2.34.1 >=20 > This looks good to me. I've looked and don't see any obvious issues in > moving x86_dtb_init() earlier in setup_arch(). But I also know the setup > ordering can be very tricky to get working correctly with a wide range of > platforms, and I don't have that expertise. > But with those caveats, >=20 > Reviewed-by: Michael Kelley Hi X86 Maintainers, Is this good to be accepted ? - Saurabh