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Date:   Fri, 11 Aug 2023 11:19:17 -0700
From:   Mike Tipton <quic_mdtipton@quicinc.com>
To:     Konrad Dybcio <konrad.dybcio@linaro.org>
CC:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Georgi Djakov <djakov@kernel.org>,
        Melody Olvera <quic_molvera@quicinc.com>,
        Odelu Kukatla <okukatla@codeaurora.org>,
        Richard Acayan <mailingradian@gmail.com>,
        David Dai <daidavid1@codeaurora.org>,
        Rob Herring <robh@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        "Luca Weiss" <luca.weiss@fairphone.com>,
        Sibi Sankar <sibis@codeaurora.org>,
        Jonathan Marek <jonathan@marek.ca>,
        Vinod Koul <vkoul@kernel.org>,
        "Marijn Suijten" <marijn.suijten@somainline.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 01/11] interconnect: qcom: qdu1000: Set ACV enable_mask
Message-ID: <20230811181917.GA1864@hu-mdtipton-lv.qualcomm.com>
References: <20230811-topic-acv-v1-0-a85b6e94f46d@linaro.org>
 <20230811-topic-acv-v1-1-a85b6e94f46d@linaro.org>
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On Fri, Aug 11, 2023 at 03:04:08PM +0200, Konrad Dybcio wrote:
> ACV expects an enable_mask corresponding to the APPS RSC, fill it in.
> 
> Fixes: 1f51339f7dd0 ("interconnect: qcom: Add QDU1000/QRU1000 interconnect driver")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  drivers/interconnect/qcom/bcm-voter.h | 2 ++
>  drivers/interconnect/qcom/qdu1000.c   | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/bcm-voter.h b/drivers/interconnect/qcom/bcm-voter.h
> index b4d36e349f3c..da92267877f9 100644
> --- a/drivers/interconnect/qcom/bcm-voter.h
> +++ b/drivers/interconnect/qcom/bcm-voter.h
> @@ -16,4 +16,6 @@ struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name);
>  void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
>  int qcom_icc_bcm_voter_commit(struct bcm_voter *voter);
>  
> +#define ACV_RSC_APPS		BIT(3)

This isn't entirely common to all chips. It's been BIT(3) for most of
history and is for all the chips in the series. But there upcoming chips
where it'll be different. There are only a finite number of ACV bits
available, so depending on the requirements they can be repurposed. We
should probably just have the raw mask defined in the target files.

> + #endif diff --git a/drivers/interconnect/qcom/qdu1000.c
> b/drivers/interconnect/qcom/qdu1000.c index bf800dd7d4ba..c504bf348294
> 100644 --- a/drivers/interconnect/qcom/qdu1000.c
> +++ b/drivers/interconnect/qcom/qdu1000.c
> @@ -769,6 +769,7 @@ static struct qcom_icc_node xs_sys_tcu_cfg = {
>  
>  static struct qcom_icc_bcm bcm_acv = {
>  	.name = "ACV",
> +	.enable_mask = ACV_RSC_APPS,
>  	.num_nodes = 1,
>  	.nodes = { &ebi },
>  };
> 
> -- 
> 2.41.0
>