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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id h8-20020a02cd28000000b0042b3ad1656bsm1749690jaq.45.2023.08.12.05.33.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 12 Aug 2023 05:33:10 -0700 (PDT) Sender: Guenter Roeck Message-ID: Date: Sat, 12 Aug 2023 05:33:09 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v3 3/3] hwmon: (pmbus/tda38640) Add workaround for bug in SVID mode Content-Language: en-US To: Naresh Solanki , Jean Delvare , krzysztof.kozlowski+dt@linaro.org Cc: linux-hwmon@vger.kernel.org, Patrick Rudolph , linux-kernel@vger.kernel.org References: <20230802193155.2170935-1-Naresh.Solanki@9elements.com> <20230802193155.2170935-3-Naresh.Solanki@9elements.com> From: Guenter Roeck In-Reply-To: <20230802193155.2170935-3-Naresh.Solanki@9elements.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 8/2/23 12:31, Naresh Solanki wrote: > From: Patrick Rudolph > > TDA38640 can operate in either PMBus mode or SVID mode. > In SVID mode, by design ENABLE pin is the only option for controlling > the output rail. > > In scenarios that utilizes the chip in SVID mode with ENABLE pin either > grounded or tied to logic high & software control is desired then use > dt property 'infineon,en-svid-control' to enable the below workaround. > > The workaround utilizes ENABLE pin polarity flipping to control > output rail. > > If property 'infineon,en-svid-control' is specified then > determine if chip is in SVID mode by checking BIT15 of MTP memory offset > 0x44 as described in the datasheet. > > If chip is in SVID mode then apply the workaround by > 1. Determine EN pin level > 2. Maps BIT7 of OPERATION(01h) to EN_PIN_POLARITY(BIT1) of > PB_ON_OFF_CONFIG. > > Signed-off-by: Patrick Rudolph > Signed-off-by: Naresh Solanki For my reference: Reviewed-by: Guenter Roeck We still have to wait for dt patch approval. Guenter