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From:   Gowthami Thiagarajan <gthiagarajan@marvell.com>
To:     <will@kernel.org>, <mark.rutland@arm.com>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <devicetree@vger.kernel.org>
CC:     <sgoutham@marvell.com>, <bbhushan2@marvell.com>,
        <lcherian@marvell.com>,
        Gowthami Thiagarajan <gthiagarajan@marvell.com>
Subject: [PATCH v2 4/6] dt-bindings: perf: Add Marvell Odyssey LLC-TAD pmu
Date:   Sat, 12 Aug 2023 19:55:16 +0530
Message-ID: <20230812142518.778259-5-gthiagarajan@marvell.com>
In-Reply-To: <20230812142518.778259-1-gthiagarajan@marvell.com>
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Add binding documentation for Marvell Odyssey LLC-TAD performance
monitor unit

Signed-off-by: Gowthami Thiagarajan <gthiagarajan@marvell.com>
---

v1->v2
- Changed DT binding file name to match with compatible
- Added respective document in MAINTAINERS

 .../perf/marvell,odyssey-tad-pmu.yaml         | 63 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml

diff --git a/Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml b/Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml
new file mode 100644
index 000000000000..a1b9ee71e5f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/marvell,odyssey-tad-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Odyssey LLC-TAD performance monitor
+
+maintainers:
+  - Gowthami Thiagarajan <gthiagarajan@marvell.com>
+
+description: |
+  The Tag-and-Data units (TADs) maintain coherence and contain CN10K
+  shared on-chip last level cache (LLC). The tad pmu measures the
+  performance of last-level cache. Each tad pmu supports up to eight
+  counters.
+
+  The DT setup comprises of number of tad blocks, the sizes of pmu
+  regions, tad blocks and overall base address of the HW.
+
+properties:
+  compatible:
+    const: marvell,odyssey-tad-pmu
+
+  reg:
+    maxItems: 1
+
+  marvell,tad-cnt:
+    description: specifies the number of tads on the soc
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  marvell,tad-page-size:
+    description: specifies the size of each tad page
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  marvell,tad-pmu-page-size:
+    description: specifies the size of page that the pmu uses
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+  - compatible
+  - reg
+  - marvell,tad-cnt
+  - marvell,tad-page-size
+  - marvell,tad-pmu-page-size
+
+additionalProperties: false
+
+examples:
+  - |
+
+    tad {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pmu@87e22b030000 {
+            compatible = "marvell,odyssey-tad-pmu";
+            reg = <0x87e2 0x2b030000 0x0 0x1000>;
+            marvell,tad-cnt = <1>;
+            marvell,tad-page-size = <0x1000>;
+            marvell,tad-pmu-page-size = <0x1000>;
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 70d2971b93d4..b9da1affe8b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12591,6 +12591,7 @@ M:	Bharat Bhushan <bbhushan2@marvell.com>
 M:	Linu Cherian <lcherian@marvell.com>
 M:	George Cherian <gcherian@marvell.com>
 S:	Supported
+F:	Documentation/devicetree/bindings/perf/marvell,odyssey-tad-pmu.yaml
 F:	drivers/perf/marvell_odyssey_tad_pmu.c
 
 MARVELL PRESTERA ETHERNET SWITCH DRIVER
-- 
2.25.1