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Reply-To: wens@csie.org
From:   Chen-Yu Tsai <wens@csie.org>
Date:   Sun, 13 Aug 2023 12:13:09 +0800
Message-ID: <CAGb2v66g1On2uy0_15ZA5-uXcrLSg7V-tsw8zLo=tUY_HUW00g@mail.gmail.com>
Subject: Re: [PATCH] riscv: dts: allwinner: d1: Specify default CAN pins
To:     =?UTF-8?Q?Jernej_=C5=A0krabec?= <jernej.skrabec@gmail.com>
Cc:     linux-sunxi@lists.linux.dev, John Watts <contact@jookia.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Samuel Holland <samuel@sholland.org>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
        Maksim Kiselev <bigunclemax@gmail.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        mkl@pengutronix.de
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On Fri, Aug 4, 2023 at 4:59 AM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
>
> /cc Marc
>
> Dne ponedeljek, 31. julij 2023 ob 04:36:59 CEST je John Watts napisal(a):
> > There are only one set of CAN pins available on these chips.
> > Specify these as the default to avoid redundancy in board device trees.
> >
> > Signed-off-by: John Watts <contact@jookia.org>
> > ---
> >  arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index
> > 4086c0cc0f9d..b27c3fc13b0d 100644
> > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> > @@ -898,6 +898,8 @@ can0: can@2504000 {
> >                       interrupts = <SOC_PERIPHERAL_IRQ(21)
> IRQ_TYPE_LEVEL_HIGH>;
> >                       clocks = <&ccu CLK_BUS_CAN0>;
> >                       resets = <&ccu RST_BUS_CAN0>;
> > +                     pinctrl-names = "default";
> > +                     pinctrl-0 = <&can0_pins>;
> >                       status = "disabled";
> >               };
>
> pinctrl-names and pinctrl-0 are usually at the top. However, since there is no
> hard rule (I've seen it mixed), I'm fine with it.

AFAIK this only applies to board files where there are mostly none of the
resource (clocks, reg, resets, interrupts) properties. OOTH the compatible
property is always the first property. I would normally put the pinctrl
stuff after the internal resources, since it is an external property.
In the SoC dtsi files, they would end up after the resource properties
I mentioned above, and before the "status" property.

ChenYu

> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
>
> Since original DT node entry goes through netdev tree, this should be picked
> there or it can be dropped there and I pick both patches or I can pick patch
> for later kernel version.
>
> Best regards,
> Jernej
>
> >
> > @@ -907,6 +909,8 @@ can1: can@2504400 {
> >                       interrupts = <SOC_PERIPHERAL_IRQ(22)
> IRQ_TYPE_LEVEL_HIGH>;
> >                       clocks = <&ccu CLK_BUS_CAN1>;
> >                       resets = <&ccu RST_BUS_CAN1>;
> > +                     pinctrl-names = "default";
> > +                     pinctrl-0 = <&can1_pins>;
> >                       status = "disabled";
> >               };
> >       };
>
>
>
>