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From:   Abel Vesa <abel.vesa@linaro.org>
To:     abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
        shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de,
        festevam@gmail.com, "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc:     linux-imx@nxp.com, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        Ye Li <ye.li@nxp.com>, Peng Fan <peng.fan@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>
Subject: Re: [PATCH 1/2] clk: imx: pllv4: Fix SPLL2 MULT range
Date:   Mon, 14 Aug 2023 13:10:02 +0300
Message-Id: <169200755846.527063.15298642342561865531.b4-ty@linaro.org>
In-Reply-To: <20230625123340.4067536-1-peng.fan@oss.nxp.com>
References: <20230625123340.4067536-1-peng.fan@oss.nxp.com>
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On Sun, 25 Jun 2023 20:33:39 +0800, Peng Fan (OSS) wrote:
> The SPLL2 on iMX8ULP is different with other frac PLLs, it can
> support VCO from 650Mhz to 1Ghz. According to RM, the MULT is
> using a range from 27 to 54, not some fixed values. If using
> current PLL implementation, some clock rate can't be supported.
> 
> Fix the issue by adding new type for the SPLL2 and use MULT range
> to replace MULT table
> 
> [...]

Applied, thanks!

[1/2] clk: imx: pllv4: Fix SPLL2 MULT range
      commit: 3f0cdb945471f1abd1cf4d172190e9c489c5052a
[2/2] clk: imx: imx8ulp: update SPLL2 type
      commit: 7653a59be8af043adc4c09473975a860e6055ff9

Best regards,
-- 
Abel Vesa <abel.vesa@linaro.org>