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From:   Adam Ford <aford173@gmail.com>
Date:   Mon, 14 Aug 2023 06:49:06 -0500
Message-ID: <CAHCN7xKysFVRq0gkp8+VG_NNs1cijacbeDs4D2JDcZ-RucGUBw@mail.gmail.com>
Subject: Re: [PATCH 1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks
To:     Lucas Stach <l.stach@pengutronix.de>
Cc:     linux-arm-kernel@lists.infradead.org, aford@beaconembedded.com,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
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On Mon, Aug 14, 2023 at 3:22=E2=80=AFAM Lucas Stach <l.stach@pengutronix.de=
> wrote:
>
> Am Sonntag, dem 13.08.2023 um 11:29 -0500 schrieb Adam Ford:
> > A previous patch to remove the Audio clocks from the main clock node
> > was intended to force people to setup the audio PLL clocks per board
> > instead of having a common set of rates since not all boards may use
> > the various audio PLL clocks for audio devices.
> >
> > Unfortunately, with this parenting removed, the SDMA2 and SDMA3
> > clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled
> > via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT,
> > and that clock is enabled by pgc_audio.
> >
> > Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz
> > AHB, always 1:1 mode, to make sure there is enough throughput for all
> > the audio use cases."
> >
> > Instead of cluttering the clock node, place the clock rate and parent
> > information into the pgc_audio node.
> >
> > With the parenting and clock rates restored for  IMX8MP_CLK_AUDIO_AHB,
> > and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at
> > 400MHz again.
> >
> Note that 800MHz for the AXI clock is overdrive mode for the chip. For
> other i.MX8M* chips we tried to have the nominal drive rates as
> assigned rates in DT. With the i.MX8MP it's currently a wild mix and
> most of the AXI clocks are set to OD rates, so I won't reject this
> patch based on this.
>
> Most boards run the DRAM at DDR4-4000, which already requires OD
> voltages, so there isn't much point in trying to stick to ND rates on
> those boards. We should probably do some consolidation here and come up
> with a proper policy for the i.MX8MP soon.

I didn't realize 800MHz was OD.  I just set it to the rate that it was
before the previous patch.  I think the defaults should be ND, and let
boards who need OD set them.  Unless someone objects, I'll submit a
V2.

adam
>
> > Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks=
 from CCM node")
> > Signed-off-by: Adam Ford <aford173@gmail.com>
>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
>
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boo=
t/dts/freescale/imx8mp.dtsi
> > index 6f2f50e1639c..408b0c4ec4f8 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -790,6 +790,12 @@ pgc_audio: power-domain@5 {
> >                                               reg =3D <IMX8MP_POWER_DOM=
AIN_AUDIOMIX>;
> >                                               clocks =3D <&clk IMX8MP_C=
LK_AUDIO_ROOT>,
> >                                                        <&clk IMX8MP_CLK=
_AUDIO_AXI>;
> > +                                             assigned-clocks =3D <&clk=
 IMX8MP_CLK_AUDIO_AHB>,
> > +                                                               <&clk I=
MX8MP_CLK_AUDIO_AXI_SRC>;
> > +                                             assigned-clock-parents =
=3D  <&clk IMX8MP_SYS_PLL1_800M>,
> > +                                                                      =
 <&clk IMX8MP_SYS_PLL1_800M>;
> > +                                             assigned-clock-rates =3D =
<400000000>,
> > +                                                                    <8=
00000000>;
> >                                       };
> >
> >                                       pgc_gpu2d: power-domain@6 {
>