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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f10-20020a056a00228a00b006768627bc5asi8277798pfe.199.2023.08.14.06.58.12; Mon, 14 Aug 2023 06:58:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbjHNNci (ORCPT + 99 others); Mon, 14 Aug 2023 09:32:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229490AbjHNNcd (ORCPT ); Mon, 14 Aug 2023 09:32:33 -0400 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03A95D1 for ; Mon, 14 Aug 2023 06:32:32 -0700 (PDT) Received: from dggpeml500002.china.huawei.com (unknown [172.30.72.55]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4RPZxp2MW3z2BdR7; Mon, 14 Aug 2023 21:29:34 +0800 (CST) Received: from [10.67.103.44] (10.67.103.44) by dggpeml500002.china.huawei.com (7.185.36.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Mon, 14 Aug 2023 21:32:29 +0800 Subject: Re: [PATCH 1/2] coresight: trbe: Fix TRBE potential sleep in atomic context To: Suzuki K Poulose , Junhao He , , , , References: <20230814093813.19152-1-hejunhao3@huawei.com> <20230814093813.19152-2-hejunhao3@huawei.com> <37e36bde-fc70-6d2d-8dec-28e572f618cc@arm.com> CC: , , , , From: hejunhao Message-ID: <4049aee1-7f4d-5a54-ce27-7d802ae9616d@huawei.com> Date: Mon, 14 Aug 2023 21:32:29 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <37e36bde-fc70-6d2d-8dec-28e572f618cc@arm.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.103.44] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To dggpeml500002.china.huawei.com (7.185.36.158) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Suzuki On 2023/8/14 18:34, Suzuki K Poulose wrote: > Hi Junhao > > On 14/08/2023 10:38, Junhao He wrote: >> smp_call_function_single() will allocate an IPI interrupt vector to >> the target processor and send a function call request to the interrupt >> vector. After the target processor receives the IPI interrupt, it will >> execute arm_trbe_remove_coresight_cpu() call request in the interrupt >> handler. >> >> According to the device_unregister() stack information, if other process >> is useing the device, the down_write() may sleep, and trigger deadlocks >> or unexpected errors. >> >> arm_trbe_remove_coresight_cpu >> coresight_unregister >> device_unregister >> device_del >> kobject_del >> __kobject_del >> sysfs_remove_dir >> kernfs_remove >> down_write ---------> it may sleep >> >> Add a helper arm_trbe_disable_cpu() to disable TRBE precpu irq and reset >> per TRBE. >> Simply call arm_trbe_remove_coresight_cpu() directly without useing the >> smp_call_function_single(), which is the same as registering the TRBE >> coresight device. >> >> Fixes: 3fbf7f011f24 ("coresight: sink: Add TRBE driver") >> Signed-off-by: Junhao He >> --- >> drivers/hwtracing/coresight/coresight-trbe.c | 35 +++++++++++--------- >> 1 file changed, 20 insertions(+), 15 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c >> b/drivers/hwtracing/coresight/coresight-trbe.c >> index 7720619909d6..ce1e6f537b8d 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -1225,6 +1225,17 @@ static void arm_trbe_enable_cpu(void *info) >> enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE); >> } >> +static void arm_trbe_disable_cpu(void *info) >> +{ >> + struct trbe_drvdata *drvdata = info; >> + struct trbe_cpudata *cpudata = this_cpu_ptr(drvdata->cpudata); >> + >> + disable_percpu_irq(drvdata->irq); >> + trbe_reset_local(cpudata); >> + cpudata->drvdata = NULL; >> +} >> + >> + >> static void arm_trbe_register_coresight_cpu(struct trbe_drvdata >> *drvdata, int cpu) >> { >> struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); >> @@ -1326,18 +1337,12 @@ static void arm_trbe_probe_cpu(void *info) >> cpumask_clear_cpu(cpu, &drvdata->supported_cpus); >> } >> -static void arm_trbe_remove_coresight_cpu(void *info) >> +static void arm_trbe_remove_coresight_cpu(struct trbe_drvdata >> *drvdata, int cpu) >> { >> - int cpu = smp_processor_id(); >> - struct trbe_drvdata *drvdata = info; >> - struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); >> struct coresight_device *trbe_csdev = >> coresight_get_percpu_sink(cpu); >> - disable_percpu_irq(drvdata->irq); >> - trbe_reset_local(cpudata); >> if (trbe_csdev) { >> coresight_unregister(trbe_csdev); >> - cpudata->drvdata = NULL; >> coresight_set_percpu_sink(cpu, NULL); > > I am a bit concerned about "resetting" the sink from a different CPU. > Could we instead, schedule a delayed work to unregister the trbe_csdev? Yes, I will try to do that. Sorry for my following questions. As you mean, do we need to take the same care when setting the percpu sink in the register trbe_csdev ? Best regards, Junhao. > > >> } >> } >> @@ -1366,8 +1371,12 @@ static int arm_trbe_remove_coresight(struct >> trbe_drvdata *drvdata) >> { >> int cpu; >> - for_each_cpu(cpu, &drvdata->supported_cpus) >> - smp_call_function_single(cpu, arm_trbe_remove_coresight_cpu, >> drvdata, 1); >> + for_each_cpu(cpu, &drvdata->supported_cpus) { >> + if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> + smp_call_function_single(cpu, arm_trbe_disable_cpu, >> drvdata, 1); >> + if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> + arm_trbe_remove_coresight_cpu(drvdata, cpu); >> + } >> free_percpu(drvdata->cpudata); >> return 0; >> } >> @@ -1406,12 +1415,8 @@ static int arm_trbe_cpu_teardown(unsigned int >> cpu, struct hlist_node *node) >> { >> struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct >> trbe_drvdata, hotplug_node); >> - if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) { >> - struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, >> cpu); >> - >> - disable_percpu_irq(drvdata->irq); >> - trbe_reset_local(cpudata); >> - } >> + if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) >> + arm_trbe_disable_cpu(drvdata); >> return 0; >> } > > > . >