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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id i64-20020a0df843000000b005704c4d3579sm3954179ywf.40.2023.08.16.04.36.27 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Aug 2023 04:36:27 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-58c4f61ca12so25047427b3.3 for ; Wed, 16 Aug 2023 04:36:27 -0700 (PDT) X-Received: by 2002:a25:da02:0:b0:d07:3fb6:c00d with SMTP id n2-20020a25da02000000b00d073fb6c00dmr2398620ybf.12.1692185787100; Wed, 16 Aug 2023 04:36:27 -0700 (PDT) MIME-Version: 1.0 References: <0f8ac07472f4161c71247742acb2303f9cf91396.1692113438.git.geert+renesas@glider.be> <2e076cb5-1e31-10b2-9f33-79a825ac9c11@arm.com> In-Reply-To: <2e076cb5-1e31-10b2-9f33-79a825ac9c11@arm.com> From: Geert Uytterhoeven Date: Wed, 16 Aug 2023 13:36:15 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] perf: ARM_SMMU_V3_PMU should depend on ARM_SMMU_V3 To: Robin Murphy Cc: Will Deacon , Mark Rutland , Jean-Philippe Brucker , Vincent Whitchurch , Joerg Roedel , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Robin, On Wed, Aug 16, 2023 at 1:23 PM Robin Murphy wrote: > On 2023-08-15 16:36, Geert Uytterhoeven wrote: > > There is no point in monitoring transactions passing through the SMMU > > when ARM Ltd. System MMU Version 3 (SMMUv3) Support is disabled. > > Hence replace the dependency on ARM64 by a dependency on ARM_SMMU_V3 > > (which implies the former). > > > > Signed-off-by: Geert Uytterhoeven > > --- > > This caught my eye after commit 7c3f204e544dfa37 ("perf/smmuv3: Remove > > build dependency on ACPI") in arm64/for-next/core. > > > > Perhaps my understanding is wrong? Is there anything to monitor when > > ARM_SMMU_V3=n? > > Yes, at least TBU event 1 still counts bypass transactions even when the > SMMU is disabled, so PMCGs can be useful as basic traffic monitors in > their own right. Plus the original design intent was that PMCGs may also > be implemented by other things that interact with the SMMU, like > ATS-capable PCIe root complexes, or devices with their own internal > TLBs, thus they could potentially count any manner of > implementation-defined events that aren't necessarily related to SMMU > translation. Thanks for the explanation! Hereby I withdraw my patch. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds