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Date:   Thu, 17 Aug 2023 12:54:05 +0200
From:   Maxime Ripard <mripard@kernel.org>
To:     Jayesh Choudhary <j-choudhary@ti.com>
Cc:     nm@ti.com, vigneshr@ti.com, afd@ti.com, rogerq@kernel.org,
        s-vadapalli@ti.com, kristo@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        a-bhatia1@ti.com, r-ravikumar@ti.com, sabiya.d@ti.com,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v9 3/5] arm64: dts: ti: k3-j784s4-main: Add DSS and
 DP-bridge node
Message-ID: <aqfx7fj446gkyirhsiwijiuilhoao4hexmpjfxu4gojpujhbib@2wqzjuh3yz46>
References: <20230803080441.367341-1-j-choudhary@ti.com>
 <20230803080441.367341-4-j-choudhary@ti.com>
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Hi,

On Thu, Aug 03, 2023 at 01:34:39PM +0530, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@ti.com>
>=20
> Add DSS and DP-bridge node for J784S4 SoC. DSS IP in J784S4 is
> same as DSS IP in J721E, so same compatible is being used.
> The DP is Cadence MHDP8546.
>=20
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> [j-choudhary@ti.com: move dss & mhdp node together in main, fix dss node]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 63 ++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot=
/dts/ti/k3-j784s4-main.dtsi
> index 446d7efa715f..824312b9ef9f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1741,4 +1741,67 @@ c71_3: dsp@67800000 {
>  		resets =3D <&k3_reset 40 1>;
>  		firmware-name =3D "j784s4-c71_3-fw";
>  	};
> +
> +	mhdp: bridge@a000000 {
> +		compatible =3D "ti,j721e-mhdp8546";
> +		reg =3D <0x0 0xa000000 0x0 0x30a00>,
> +		      <0x0 0x4f40000 0x0 0x20>;
> +		reg-names =3D "mhdptx", "j721e-intg";
> +		clocks =3D <&k3_clks 217 11>;
> +		interrupt-parent =3D <&gic500>;
> +		interrupts =3D <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
> +		power-domains =3D <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
> +		status =3D "disabled";
> +
> +		dp0_ports: ports {
> +			#address-cells =3D <1>;
> +			#size-cells =3D <0>;
> +		};
> +	};
> +
> +	dss: dss@4a00000 {
> +		compatible =3D "ti,j721e-dss";

As far as I can see, this compatible limits the (DPI) pixel clock to
160MHz, but the TRM seems to mention that it's 600MHz?

Is it expected?

Maxime

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